77V011
Abstract: 77V400 800B 800E 801C CRC-10 IDT77V011 IDT77V400
Text: DATA PATH INTERFACE DPI TO UTOPIA LEVEL 2 TRANSLATION DEVICE Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Single chip interface between multiple UTOPIA PHYs and a single Data Path Interface (DPI). Ideal for xDSL DSLAM and 25Mbps switching applications. Supports ATM Forum UTOPIA Level 2 interface in both 8-bit and 16bit modes.
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Original
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PDF
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25Mbps
16bit
IDT77V011
50MHz.
I5/15/00
5348tbl15
77V011
77V400
800B
800E
801C
CRC-10
IDT77V011
IDT77V400
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mbus
Abstract: SK 8022 ace dsc hen nu SM 8002 C
Text: IDT77V011 DATA PATH INTERFACE DPI TO UTOPIA LEVEL 2 TRANSLATION DEVICE Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Single chip interface between multiple UTOPIA PHYs and a single Data Path Interface (DPI). Ideal for xDSL DSLAM and 25Mbps switching applications.
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Original
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PDF
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IDT77V011
25Mbps
16bit
50MHz.
5248drw26a
32-bytes
31-bytes.
5348drw18.
5348tbl28.
mbus
SK 8022
ace dsc hen nu
SM 8002 C
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70P3337
Abstract: 70P3307
Text: PRELIMINARY DATASHEET IDT70P3307 IDT70P3337 1024K/512K x18 SYNCHRONOUS DUAL QDR-IITM Features ◆ 18Mb Density 1024K x 18 – Also available 9Mb Density (512K x 18) QDR-II x 18 Burst-of-2 Interface – Commercial: 233MHz, 250MHz Separate, Independent Read and Write Data Ports
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Original
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PDF
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IDT70P3307
IDT70P3337
1024K/512K
1024K
233MHz,
250MHz
18/9Mb
IDT70P3307/70P3337
70P3337
70P3307
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Untitled
Abstract: No abstract text available
Text: DATA PATH INTERFACE DPI TO UTOPIA LEVEL 2 TRANSLATION DEVICE Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Single chip interface between multiple UTOPIA PHYs and a single Data Path Interface (DPI). Ideal for xDSL DSLAM and 25Mbps switching applications. Supports ATM Forum UTOPIA Level 2 interface in both 8-bit and 16bit modes.
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Original
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PDF
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IDT77V011
25Mbps
16bit
50MHz.
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Untitled
Abstract: No abstract text available
Text: DATA PATH INTERFACE DPI TO UTOPIA LEVEL 1 HEADER TRANSLATION DEVICE Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ 8, 12, 24, 28 or 32-bit ATM header lookup. Ideal for DSLAM designs utilizing SWITCHStAR where full header access is needed. Supports VPI Tunneling
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Original
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PDF
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32-bit
IDT77V012
66MHz.
77V012,
5347drw58
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IDT71V432
Abstract: No abstract text available
Text: PRELIMINARY 32K x 32 CacheRAM IDT71V432 3.3V SYNCHRONOUS SRAM WITH BURST COUNTER, SINGLE CYCLE DESELECT Integrated Device Technology, Inc. FEATURES: • 32K x 32 memory configuration • Supports high performance system speed - 100 MHz 5ns Clock-to-Data Access in Pipelined Mode
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Original
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PDF
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IDT71V432
MT58LC32K32D7LG-XX)
100-pin
IDT71V432
71V432
PK100-1)
71V432S5PF
71V432S6PF
71V432S7PF
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71V536
Abstract: No abstract text available
Text: PRELIMINARY 32K x 36 CacheRAM IDT71V536 3.3V SYNCHRONOUS BURST SRAM WITH PIPELINED OUTPUT Integrated Device Technology, Inc. FEATURES: • 32K x 36 memory configuration • Supports high performance system speed - 120 MHz 5.0ns Clock-to-Data Access . • LBO input selects interleaved or linear burst mode
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Original
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PDF
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IDT71V536
100-pin
IDT71V536
648-bit
71V536
PK100-1)
71V536
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sm 8013
Abstract: 77V011 77V400 800B 800E 801C CRC-10 IDT77V011 IDT77V400
Text: DATA PATH INTERFACE DPI TO UTOPIA LEVEL 2 TRANSLATION DEVICE Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Single chip interface between multiple UTOPIA PHYs and a single Data Path Interface (DPI). Ideal for xDSL DSLAM and 25Mbps switching applications. Supports ATM Forum UTOPIA Level 2 interface in both 8-bit and 16bit modes.
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Original
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PDF
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25Mbps
16bit
IDT77V011
50MHz.
5348drw45
sm 8013
77V011
77V400
800B
800E
801C
CRC-10
IDT77V011
IDT77V400
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Untitled
Abstract: No abstract text available
Text: IDT71P74204 IDT71P74104 IDT71P74804 IDT71P74604 18Mb Pipelined QDR II SRAM Burst of 4 Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Description 18Mb Density 2Mx8, 2Mx9, 1Mx18, 512kx36 Separate, Independent Read and Write Data Ports Supports concurrent transactions
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Original
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PDF
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IDT71P74204
IDT71P74104
IDT71P74804
IDT71P74604
IDT71P74204
71P74104
71P74804
71P74604
36-Bit)
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intel 8008 cpu
Abstract: No abstract text available
Text: DATA PATH INTERFACE DPI TO UTOPIA LEVEL 2 TRANSLATION DEVICE Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Single chip interface between multiple UTOPIA PHYs and a single Data Path Interface (DPI). Ideal for xDSL DSLAM and 25Mbps switching applications. Supports ATM Forum UTOPIA Level 2 interface in both 8-bit and 16bit modes.
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Original
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PDF
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IDT77V011
25Mbps
16bit
50MHz.
5348tbl15
intel 8008 cpu
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Q13L
Abstract: 70P3337 CQX 89 IDT70P3307 IDT70P3337 diode d5r 70P3307
Text: PRELIMINARY DATASHEET IDT70P3307 IDT70P3337 1024K/512K x18 SYNCHRONOUS DUAL QDR-IITM Features ◆ 18Mb Density 1024K x 18 – Also available 9Mb Density (512K x 18) QDR-II x 18 Burst-of-2 Interface – Commercial: 233MHz, 250MHz Separate, Independent Read and Write Data Ports
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Original
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PDF
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IDT70P3307
IDT70P3337
1024K/512K
1024K
233MHz,
250MHz
de024
70P3337
drw17
Q13L
CQX 89
IDT70P3307
IDT70P3337
diode d5r
70P3307
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IDT71V432
Abstract: No abstract text available
Text: PRELIMINARY 32K x 32 CacheRAM IDT71V432 3.3V SYNCHRONOUS SRAM WITH BURST COUNTER, SINGLE CYCLE DESELECT Integrated Device Technology, Inc. FEATURES: • 32K x 32 memory configuration • Supports high performance system speed - 83 MHz 6ns Clock-to-Data Access in Pipelined Mode
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Original
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PDF
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IDT71V432
MT58LC32K32D7LG-XX)
100-pin
IDT71V432
71V432
PK100-1)
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6AD5
Abstract: No abstract text available
Text: DATA PATH INTERFACE DPI TO UTOPIA LEVEL 1 HEADER TRANSLATION DEVICE Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ 8, 12, 24, 28 or 32-bit ATM header lookup. Ideal for network side of SWITCHStAR DSLAM designs where full header access is needed. Supports VPI Tunneling
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Original
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PDF
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IDT77V012
32-bit
66MHz.
77V012,
search347drw58
31-byte
6AD5
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INTEGRATED DEVICE TECHNOLOGY 71V432
Abstract: IDT71V432
Text: PRELIMINARY 32K x 32 CacheRAM IDT71V432 3.3V SYNCHRONOUS SRAM WITH INTERLEAVED/LINEAR BURST COUNTER Integrated Device Technology, Inc. FEATURES: • 32K x 32 memory configuration • Supports high performance system speed - 66 MHz 7ns Clock-to-Data Access in Pipelined Mode
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Original
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PDF
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IDT71V432
100-pin
IDT71V432
576-bit
71V432
PK100-1)
INTEGRATED DEVICE TECHNOLOGY 71V432
|
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IDT71P74604
Abstract: IDT71P74804 6111T 71P74604
Text: IDT71P74804 IDT71P74604 18Mb Pipelined QDR II SRAM Burst of 4 Features • • • • • • • • • • • • Description 18Mb Density 1Mx18, 512kx36 Separate, Independent Read and Write Data Ports - Supports concurrent transactions Dual Echo Clock Output
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Original
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PDF
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IDT71P74804
IDT71P74604
1Mx18,
512kx36)
71P74604
36-Bit)
71P4204
71P4104
250MHz
IDT71P74604
IDT71P74804
6111T
71P74604
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intel 8008
Abstract: No abstract text available
Text: DATA PATH INTERFACE DPI TO UTOPIA LEVEL 2 TRANSLATION DEVICE Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Single chip interface between multiple UTOPIA PHYs and a single Data Path Interface (DPI). Ideal for xDSL DSLAM and 25Mbps switching applications. Supports ATM Forum UTOPIA Level 2 interface in both 8-bit and 16bit modes.
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Original
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PDF
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IDT77V011
25Mbps
16bit
50MHz.
intel 8008
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TBL27
Abstract: No abstract text available
Text: DATA PATH INTERFACE DPI TO UTOPIA LEVEL 2 TRANSLATION DEVICE Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Single chip interface between multiple UTOPIA PHYs and a single Data Path Interface (DPI). Ideal for xDSL DSLAM and 25Mbps switching applications. Supports ATM Forum UTOPIA Level 2 interface in both 8-bit and 16bit modes.
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Original
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PDF
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IDT77V011
25Mbps
16bit
50MHz.
5348tbl15
TBL27
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ty 8016
Abstract: 10.7 HY SM 8002 sm 8013 TY 8004 Cross Reference NTE datasheet ty 8016 77V011 77V400 800B
Text: DATA PATH INTERFACE DPI TO UTOPIA LEVEL 2 TRANSLATION DEVICE Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Single chip interface between multiple UTOPIA PHYs and a single Data Path Interface (DPI). Ideal for xDSL DSLAM and 25Mbps switching applications. Supports ATM Forum UTOPIA Level 2 interface in both 8-bit and 16bit modes.
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Original
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PDF
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25Mbps
16bit
IDT77V011
50MHz.
5348drw45
ty 8016
10.7 HY
SM 8002
sm 8013
TY 8004
Cross Reference NTE
datasheet ty 8016
77V011
77V400
800B
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ELLS 110
Abstract: SM 8002 DSLAM ALU sm 8013 TS-6 77V012 800B IDT77V012 IDT77V400 256Kx32bit
Text: DATA PATH INTERFACE DPI TO UTOPIA LEVEL 1 HEADER TRANSLATION DEVICE Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ 8, 12, 24, 28 or 32-bit ATM header lookup. Ideal for DSLAM designs utilizing SWITCHStAR where full header access is needed. Supports VPI Tunneling
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Original
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PDF
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32-bit
IDT77V012
66MHz.
77V012,
5347drw58
ELLS 110
SM 8002
DSLAM ALU
sm 8013
TS-6
77V012
800B
IDT77V012
IDT77V400
256Kx32bit
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Q11L
Abstract: 70P3337 CQX 89 IDT70P3307 IDT70P3337 RM-576 Q15L tbl17 BW1R q11r
Text: PRELIMINARY DATASHEET IDT70P3307 IDT70P3337 1024K/512K x18 SYNCHRONOUS DUAL QDR-IITM Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ 18Mb Density 1024K x 18 – Also available 9Mb Density (512K x 18) QDR-II x 18 Burst-of-2 Interface – Commercial: 233MHz, 250MHz
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Original
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PDF
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IDT70P3307
IDT70P3337
1024K/512K
1024K
233MHz,
250MHz
18/9Mb
IDT70P3307/70P3337
Q11L
70P3337
CQX 89
IDT70P3307
IDT70P3337
RM-576
Q15L
tbl17
BW1R
q11r
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SM 8002 C
Abstract: 77V012 800B IDT77155 IDT77V012 IDT77V400 DSLAM ALU
Text: DATA PATH INTERFACE DPI TO UTOPIA LEVEL 1 HEADER TRANSLATION DEVICE Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ 8, 12, 24, 28 or 32-bit ATM header lookup. Ideal for network side of SWITCHStAR DSLAM designs where full header access is needed. Supports VPI Tunneling
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Original
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PDF
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32-bit
IDT77V012
66MHz.
77Vreleased
31-byte
SM 8002 C
77V012
800B
IDT77155
IDT77V012
IDT77V400
DSLAM ALU
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INTEGRATED DEVICE TECHNOLOGY 71V432
Abstract: IDT71V432S7 IDT71V432
Text: PRELIMINARY 32K x 32 CacheRAM IDT71V432 3.3V SYNCHRONOUS SRAM WITH INTERLEAVED/LINEAR BURST COUNTER Integrated Device Technology, Inc. FEATURES: • 32K x 32 memory configuration • Supports high performance system speed - 66 MHz 7ns Clock-to-Data Access in Pipelined Mode
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Original
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PDF
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IDT71V432
100-pin
IDT71V432
576-bit
71V432
PK100-1)
INTEGRATED DEVICE TECHNOLOGY 71V432
IDT71V432S7
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IDT71P74204
Abstract: IDT71P74604 IDT71P74804 6111T
Text: IDT71P74804 IDT71P74604 18Mb Pipelined QDR II SRAM Burst of 4 Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Description 18Mb Density 1Mx18, 512kx36 Separate, Independent Read and Write Data Ports Supports concurrent transactions Dual Echo Clock Output
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Original
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PDF
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IDT71P74804
IDT71P74604
1Mx18,
512kx36)
IDT71P74804
IDT71P74604
71P74804
71P74604
36-Bit)
71P74204
IDT71P74204
6111T
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71V536
Abstract: No abstract text available
Text: PRELIMINARY 32K X 36 CacheRAM IDT71V536 3.3V SYNCHRONOUS BURST SRAM WITH PIPELINED OUTPUT I n t e g r a t e d D e v iz e T e c h n o lo g y , l i e . FEATURES: • • • • • • • 32K x 36 m em ory configuration Supports high perform ance system speed -1 2 0 MHz
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OCR Scan
|
PDF
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IDT71V536
100-pin
492-M
71V536
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