tms4256
Abstract: TMS4266
Text: INSTR TM4256EL9, TM4256GU9 262,144 BY 9-BIT DYNAMIC BAM MODULES 7“-ifc-23-/7 25E D SEPTEMBER 1986 — REVISED M ARCH 1968 A SIC /MEMORY 262,144 x 9 Organization TM4266EL9 . . . L SMQLE-IN-UNE PACKAGE (TOP VIEWl_ Slngla 5-V Supply (10% Tolerance)
|
OCR Scan
|
PDF
|
U17ES
077GC
TM4256EL9,
TM4256GU9
-ifc-23-/7
TM4266EL9
30-Pln
TM4256EL9)
TM4266GU9)
tms4256
TMS4266
|
AX2022
Abstract: TACT2150 D6142
Text: TACT2150 512 X 8 CACHE ADDRESS COMPARATOR D 2 9 9 3 . JA N U A R Y 1 9 8 7 - R E V IS E D SEPTEM BER 1967 Address to MATCH Valid Time TACT2150-20 . . . 20 ns max TACT2150-30 . . . 30 ns max DW, JD . OR NT PACKAGE 300-Mil 24-Pin Ceramic Side-Brazed or Plastic Dual-In-Line or Small Outline
|
OCR Scan
|
PDF
|
TACT2150
300-Mil
24-Pin
AX2022
D6142
|
ltl17
Abstract: No abstract text available
Text: flTblTSS 0 0 7 7 0 0 2 0 TM4256FC1 1,048,576 BY 1B IT DYNAMIC RAM MODULE INS TR A SIC /MEMORY OCTOBER'19 9 5 —REVISED FEBRUARY 1988 BSE D 1 ,0 4 8 ,5 7 6 x 1 Organization TM 4266FC 1 . . C SINGLE-IN-LINE PACKAGE (TOP VIEW) Single 5-V Supply (10 % Tolerance)
|
OCR Scan
|
PDF
|
TM4256FC1
4266FC
22-Pin
ltl17
|
aoo8
Abstract: smd ic lv 1116 ao65 Tolerance limit for basic dimensions in ansi y14
Text: < Military 10H518 M O T O R O LA Dual 2-Wide 3-Input “OR-AND” Gate ELECTRICALLY TESTED PER: 5962-8755901 The 10H518 is a basic logic building block providing the OR/AND function, use ful in data control and digital multiplexing applications. This M ECL 10H part is a functional/pinout duplication of the standard M ECL
|
OCR Scan
|
PDF
|
10H518
10H518
10K-Compatible
10H518/BXAJC
aoo8
smd ic lv 1116
ao65
Tolerance limit for basic dimensions in ansi y14
|
TL 2272 M
Abstract: No abstract text available
Text: <g> M O T O R O L A Military 10507 Triple 2 Input Exclu sive “O R ’VExclusive “NOR” Gate ELEC TRICA LLY T E STE D PER: MIL-M-38510/06005 M The 10507 is a triple 2 input exclusive OR/NOR gate. P ll/ l/ ll • 40 m W Max/Gate No Load • tpcj = 2.8 ns typ
|
OCR Scan
|
PDF
|
MIL-M-38510/06005
10507/BXAJC
TL 2272 M
|
LC6502
Abstract: LC7060 ic la 7522 sanyo lc7560 Sanyu thd2 buzzer
Text: 0 SEMICONDUCTOR CORP 3SE D m 7 cic1707t, G O O Ö O b S wr 5 B T '7H-0& O l w 3012A ' CMOS LSI Electronic Volume Control for Graphic Equalizer $1890C The 3-chip configuration consisting of the LC7520, a controller LC7060 or general-purpose microcomputer LC6502, etc. , and a display LSI (LC7560—»LCD,
|
OCR Scan
|
PDF
|
1707t,
1890C
LC7520,
LC7060
LC6502,
LC7560--
LC7565
-10dB,
MFP24
QIP48A
LC6502
ic la 7522
sanyo lc7560
Sanyu
thd2 buzzer
|
T74LSxx
Abstract: No abstract text available
Text: SS T54LS395/ 395A Ü 4tS39S/395A 4-BIT SHIFT REGISTER WITH 3-STATE OUTPUTS DESCRIPTION The T54LS395/395A/T74LS395/395A are 4-Bit Re gisters with 3-state outputs and can operate in ei ther a synchronous parallel load or a serial shift-right mode, as determined by the Select in
|
OCR Scan
|
PDF
|
T54LS395/395A
4tS39S/395A
T54LS395/395A/T74LS395/395A
T54LSXXX
T74LSXXX
T74LSxx
|
T74LS273B1
Abstract: LS273 T54LS273D2 T74LS273C1 LHAD
Text: T54LS273 T74LS273 S S 8-BIT REGISTER WITH CLEAR DESCRIPTION The T54LS273/T74LS273 is a high speed 8-Bit Re gister. The register consists of eight D-Type Flipflops with a Common Clock and an asynchronous active LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3 inch lead spacing.
|
OCR Scan
|
PDF
|
T54LS273
T74LS273
T54LS273/T74LS273
20-pin
T74LS273B1
LS273
T54LS273D2
T74LS273C1
LHAD
|
pc014
Abstract: LS258
Text: a s QUAD 2-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS DESCRIPTION The LSTTL/MSI T54LS258/258A, T74LS258/258A s a Quad 2-Input Multiplexer with 3-state outputs. Four bits of data from two sources can be selec ted using a Common Data Select input. The four outputs present the selected data in the comple
|
OCR Scan
|
PDF
|
T54LS258/258A,
T74LS258/258A
T54LSXXXe
pc014
LS258
|
Untitled
Abstract: No abstract text available
Text: H D 74A C 168/H D 74A C 169 D escription T he H D 74A C168 and H D 74A C169 are fully syn chronous 4-stage u p /d o w n counters. The H D 74A C168 is a BCD decade c o u n te r, the H D 74A C169 is a m odulo-16 binary counter. B oth feature a preset capability for program m able opera
|
OCR Scan
|
PDF
|
HD74AC168/HD74AC169
odulo-16
|
Am2963
Abstract: No abstract text available
Text: Am29833A/Am29853A/Am29855A Parity Bus Transceivers VSS86ZUJV/V8S86ZUIV/VSC86ZUIV DISTINCTIVE CHARACTERISTICS • High-speed bidirectional bus transceivers for processor organized devices - T-R delay = 6 ns typical - Rj-Parity delay = 9 ns typical • Error flag with open-collector output
|
OCR Scan
|
PDF
|
Am29833A/Am29853A/Am29855A
VSS86ZUJV/V8S86ZUIV/VSC86ZUIV
200-mV
Am29833
Am29853
Am29855A
Am29833A
Am29853A
AIS-WCP-20M-01/88-0
Am2963
|
Untitled
Abstract: No abstract text available
Text: Am29C827/Am29C828 Am29C927/Am29C928 Am29C827/Am29C828 Am29C927/Am29C928 High-Performance CMOS Bus Buffers DISTINCTIVE CHARACTERISTICS • • • High-speed CMOS buffers and inverters - D-Y delay = 7 ns typical Low standby power JEDEC FCT-compatible specs
|
OCR Scan
|
PDF
|
Am29C827/Am29C828
Am29C927/Am29C928
200-mV
Am29C900
Am29C827
Am29C828
10-bit
|
Am29C82
Abstract: No abstract text available
Text: Am29C821 / Am29C823 Am29C921 /Am29C923 High-Performance CMOS Bus Interface Registers High-speed parallel positive edge-triggered registers with D-type flip-flops - CP-Y propagation delay = 8 ns typical • Low standby power • JEDEC FCT-compatible specs •
|
OCR Scan
|
PDF
|
Am29C821
Am29C823
Am29C921
/Am29C923
/Am29C823
Am29C921/Am29C923
10-bit)
Am29C900
Am29C82
|
29c833
Abstract: 29C933 amd 955
Text: Am29C833/Am29C853/Am29C855 Am29C933/Am29C953/Am29C955 Am29C833/Am29C853/Am29C855 Am29C933/Am29C953/Am29C955 High-Performance CMOS Parity Bus Transceivers DISTINCTIVE CHARACTERISTICS • • • • High-speed CMOS bidirectional bustransceivers - T-R delay = 6 ns typical
|
OCR Scan
|
PDF
|
Am29C833/Am29C853/Am29C855
Am29C933/Am29C953/Am29C955
Am29C855
200-mV
Am29C900
Am29C833
Am29C853
29c833
29C933
amd 955
|
|
|
TSP50C50
Abstract: TSP50C4X TSP60C19 paralell input serial output shift register
Text: TSP60C19 SPEECH DATA ROM 4.0 TSP60C19 GENERAL DESCRIPTION THE TSP60C19 IS A 256K BIT ROM FABRICATED IN CMOS TECHNOLOGY FOR LOW OPERATING AND STANDBY POWER CONSUMPTION. THE DESIGN IS OPTIMIZED FOR THE DATA STORAGE REQUIREMENTS OF SYNTHETIC SPEECH SYSTEMS BUT MAY
|
OCR Scan
|
PDF
|
TSP60C19
28-PIN
TSP50C50
TSP50C4X
paralell input serial output shift register
|
Untitled
Abstract: No abstract text available
Text: HITACHI/ LOGIC/ARRAYS/MEM HD74HCT137 TB DE 4 4 ^ 2 0 3 # 3-to-8-line Decoder/Dem ultiplexer with Address Latch | PIN ARRANGEMENT r-J-a T - , T ¡ ] Vcc B[T - B c^ - C Yi u jy. GL Yi ÏÏ]V i G L^ - A Yfl - C¡ Yi ¡ 2] Yi G i^ - Gi
|
OCR Scan
|
PDF
|
HD74HCT137
0D1D315
T-90-20
|
Untitled
Abstract: No abstract text available
Text: H I T A C H I / L O G I C / A R R A Y S / M E M H D 74H C 374 H D 74H C 534 I S D Ë J M a t a d a 1 5 1 3 fi • Octal D-type Flip-Flops with 3 -state outputs • Octal D-type Flip-Flops (with inverted 3 -state o u tp u ts ) 92D These devices are positive edge triggered flip-flo ps. The d if
|
OCR Scan
|
PDF
|
HD74HC374
HD74HC534
0D1D315
T-90-20
|
Untitled
Abstract: No abstract text available
Text: H D 74A C 165/H D 74A C T 165 # P a r a lle llo a d 8-bit Shift Register Description Pin Assignment This 8-bit serial shift register shifts data from Qa to Q h when clocked, Parallel inputs to each stage are enabled by a low level at the Shift/Load Input.
|
OCR Scan
|
PDF
|
165/H
Dia112
T-90-20
|
Untitled
Abstract: No abstract text available
Text: "HITACHI/ L O G I C / A R RA YS /M En TS D E I 4 4 ^ 5 0 3 DD Id 3 Mb 4 | .9 2 D HD74HC76 • 10346 D T ~ Ÿ é ~ â 7 -û 7 Dual J-K Flip-Flops with Preset and Clear • PIN ARRANGEMENT Each flip -flo p has independent J, K , preset, clear, and clock
|
OCR Scan
|
PDF
|
HD74HC76
0D1D315
T-90-20
|
Untitled
Abstract: No abstract text available
Text: •Quad 2-Input OR Gate Pin Assignment • O u tp u ts Source/Sink 24m A T op View D C Characteristics (unless otherwise specified) Symbol Parameter Max Icc Maximum Quiescent Supply Current 40 Icc Maximum Quiescent Supply Current 4.0 Unit Condition uA Vin = Vcc or Ground,
|
OCR Scan
|
PDF
|
T-90-20
|
Untitled
Abstract: No abstract text available
Text: Ì5 HITACHI/ LOGIC/ARRAYS/MEM DE] 4 4 ^ 5 0 3 0GlD3b3 92D HD74HC107 4 |~ V T ~ lf b ~ '0 7 - '0 7 10363 Dual J-K Flip-Flops with Clear This flip-flop is edge sensitive to the clock input and change | PIN ARRANGEMENT state on the negative going transition of the clock pulse.
|
OCR Scan
|
PDF
|
HD74HC107
0D1D315
T-90-20
|
Untitled
Abstract: No abstract text available
Text: HITACH I/ LOGIC/ARRAYS/MEfl ì n j 44Tb2D3 00104L.7 5 J~~ -> HD74HC253 92D 10467 D # Dual 4-to-l-line Data Selectors/Multiplexers with 3-state outputs r * b * 7 " X l - 5 1 T he large ou tp u t drive a n d 3-state features o f this device P IN A R R A N G E M E N T
|
OCR Scan
|
PDF
|
44Tb2D3
00104L
HD74HC253
0D1D315
T-90-20
|
Untitled
Abstract: No abstract text available
Text: HITACHI/ L O G I C / A R R A Y S / M E N 'ÎH D eJ 44^203 DOlObbb Q 10666 d 7 "-S 2 -3 Ì 92D HD74HCT640,HD74HCT643 Both the HD74HCT640 and the HD74HCT643 have one active low enable Input G , and a direction control (D IR ). When the DIR Input li high, data flow i from the A Inputi
|
OCR Scan
|
PDF
|
HD74HCT640
HD74HCT643
HD74HCT643
0D1D315
T-90-20
|
Untitled
Abstract: No abstract text available
Text: HD74A C 241 / H D 7 4 A C T 2 4 1 ' “ Description The HD74A C 241 /H D 74ACT241 is an octal buffer and line driver designed to be em ployed as a memory address driver, clock driver and busoriented transmitter or receiver which provides im proved PC board density.
|
OCR Scan
|
PDF
|
HD74A
74ACT241
HD74ACT241
T-90-20
|
