T38B Search Results

Asus MONITOR MOTHERBOARD CIRCUIT MANUAL

Abstract: T2D 83 diode gp026 st GP025 82430TX 82371EB Asus PC MOTHERBOARD CIRCUIT schematic diode T75A Asus PC MOTHERBOARD CIRCUIT MANUAL 8272A floppy disk controller block diagram
Contextual Info: PRELIMINARY DRAFT Intel Extended Temperature 82371EB PCI-TO-ISA/IDE Xcelerator PIIX4E Datasheet  Integrated 16 x 32-bit Buffer for IDE PCI Burst Transfers  Supports Glue-less “Swap-Bay” Option with Full Electrical Isolation Supported Kits for both Pentium and

Contextual Info: MF1501-02 IEEE1394 Controller S1R72805 Technical Manual NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.

Contextual Info: intJ. 82375EB PCI-EISA Bridge PCEB Provides the Bridge Between the PCI Bus and EISA Bus 32-Bit Data Paths 100% PCI and EISA Compatible — PCI and EISA Master/Slave Interface — Directly Drives 10 PCI Loads and 8 EISA Slots — Supports PCI at 25 MHz to 33 MHz

82378ib

Contextual Info: A P M Ä M ! DM iP© I^[ìfflA'irD@ N] in te i 82378IB SYSTEM I/O SIO Provides the Bridge Between the PCI Bus and ISA Bus Arbitration for PCI Devices — Four PCI Masters are Supported — Fixed, Rotating, or a Combination of the Two 100% PCI and ISA Compatible

PIR D 203 S

Abstract: BRQ TI 78 RA16 UT69R000 t37h
Contextual Info: Standard Products UT69R000 Rad-Hard MicroController Data Sheet January 1998 q Built-in 9600 baud UART q Full military operating temperature range, -55oC to +125oC, in accordance with MIL-PRF-3853 for Class Q or V q Radiation-hardened process and design; total dose

T3D 34 diode

Abstract: 82440LX Diode T3D 57 t57b T27b t59b T31C Transistor t59c ISA BUS spec t119
Contextual Info: E DATASHEET ADDENDUM 82371AB PIIX4 PCI ISA IDE Xcelerator Timing Specifications September 1997 Order Number: 290548-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions

SMD MARKING CODE A00b

Abstract: mil-std-1750a MARKING CODE A00B MIL-PRF-38510 as3 SMD Transistor MIL-STD-1750 ttl nim marking a00b SMD A009 pir chip
Contextual Info: Standard Products UT1750AR RadHard RISC Microprocessor Data Sheet May 2003 FEATURES q Operates in either RISC Reduced Instruction Set Computer mode or MIL-STD-1750A mode q Built-in multiprocessor bus arbitration and Direct Memory Access support (DMA) q Supports MIL-STD-1750A 32-bit floating-point

5757H

Abstract: A1318 U DP83905
Contextual Info: S e m i c o n d u c t o r DP83905 AT/LANTIC AT Local Area Network Twisted-Pair Interface Controller General Description Features The AT/LANTIC AT Local Area Network Twisted-pair Inter­ face Controller is a CMOS VLSI device designed for easy implementation of CSMA/CD local area networks.

epson 0x95

Abstract: CBW15 S1R72003F00B100 CBW18 equivalent transistor t205 t324 t393 transistor t349 00A1 CS01
Contextual Info: MF1495-02 USB2.0 Device Controller S1R72003 Technical Manual NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.

Contextual Info: MF1501-02 IEEE1394 Controller S1R72805 Technical Manual NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.

CHIP T395 S

Abstract: S1R72103
Contextual Info: MF1528-01 SCSI-2/IDE Interface Controller S1R72103 Technical Manual NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.

S1R72901F00A1

Abstract: MF1504-02
Contextual Info: MF1504-02 IEEE1394 Controller S1R72901 Technical Manual NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.

temperature controller CHB 402 pid

Abstract: temperature controller CHB 402 manual IC 74115 LS 74141 pin diagram of ic 7489 IC 74134 S1R72V05F00 74118 CHN 844 diode
Contextual Info: S1R72V05 Technical Manual Rev.1.3 NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material

fe3021

Abstract: 64K DRAM 80286 schematic 80286 mouse D4000-D7FFF 0F80000FFFFF 8042 keyboard controller LIM EMS 4.0 FE3010B
Contextual Info: WESTERN DIGITAL CORP “'" system s lòg' i c / 4DE D • T71fl22ä aG0bSS3 Q Hlii»C péripheral t - 5 2 ,- 3 3 - 2 - 1 FE3021 Address Bujfer and Memory Controller f SS WESTERN DIGITAL WESTERN D IG IT A L CORP 40E D ■ 1716223 OOQbSSM 2 H l i l DC FE3021

I960CA

Abstract: CRC10 RS8234 RS8250 on-demand multicast messages
Contextual Info: RS8234 ATM ServiceSAR Plus with xBR Traffic Management The RS8234 Service Segmentation and Reassembly Controller integrates ATM terminal functions, PCI Bus Master and Slave controllers, and a UTOPIA interface with service specific functions in a single package. The ServiceSAR Controller generates and

I960CA

Abstract: CN8236 CX28250EVM Bt8223
Contextual Info: CN8236 ATM ServiceSAR Plus with xBR Traffic Management The CN8236 Service Segmentation and Reassembly Controller integrates ATM terminal functions, PCI Bus Master and Slave controllers, and a UTOPIA level 1 or 2 interface with service-specific functions in a single package for AAL0, 3/4, and 5 operations.

T55B

Abstract: T71A t19c t17c t61b t58b t57b T27b t65a T3D 62
Contextual Info: 82371AB PCI ISA IDE Xcelerator PIIX4 23.0 Clock, Reset, ISA Bus, X-Bus, and Host Timing Diagrams Figure 41. Clock Timing Period High Time PCICLK, SYSCLK, OSC 2.0V 0.8V Low Time Fall Time Rise Time Figure 42. Reset Inactive Timing SUS_STAT[1:2]# t2f PCIRST#, RSTDRV

Contextual Info: RS8235 Endstation ATM ServiceSAR with xBR Traffic Management The RS8235 Service Segmentation and Reassembly Controller integrates ATM terminal functions, PCI Bus Master and Slave controllers, and a UTOPIA interface with service specific functions in a single package. The ServiceSAR Controller generates and

Contextual Info: MF1495-03 USB2.0 Device Controller S1R72003 Technical Manual NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.

Contextual Info: Â IW M 1 in te i D M ]F © fô ü iM îrO R !] 82595 ISA/PCMCIA HIGH INTEGRATION ETHERNET CONTROLLER Optimal Integration for Lowest Cost Solution — Glueless 8-Bit/ 16-Bit ISA/PCMCIA 2.0 Bus Interface — Provides Fully 802.3 Compliant AUI and TPE Serial Interface

dma controller chip

Contextual Info: in tj, 82374EB EISA SYSTEM COMPONENT ESC • Integrates EISA Compatible Bus Controller — Translates Cycles between EISA and ISA Bus — Supports EISA Burst and Standard Cycles — Supports ISA No Wait State Cycles — Supports Byte Assembly/ Disassembly for 8-, 16- and 32-Bit

Contextual Info: RS8235 Endstation ATM ServiceSAR with xBR Traffic Management The RS8235 Service Segmentation and Reassembly Controller integrates ATM terminal functions, PCI Bus Master and Slave controllers, and a UTOPIA interface with service specific functions in a single package. The ServiceSAR Controller generates and

CN8234

Abstract: BT82
Contextual Info: RS8234 ATM ServiceSAR Plus with xBR Traffic Management The RS8234 Service Segmentation and Reassembly Controller integrates ATM terminal functions, PCI Bus Master and Slave controllers, and a UTOPIA interface with service specific functions in a single package. The ServiceSAR Controller generates and

GP360

Abstract: RPX 200 GP425 T28b 2d graphics line drawing filling texture mapping CQ T4A X1Y11
Contextual Info: r CIRRUS LOGIC G r aph i cs Primitives: • Trapezoid fill for high speed graphics • Line drawing B it BLT Engine: • Three operand BitBLT source, pattern, and destination • Automatic pattern (texture) replication Page M e mo r y Interface: • XY to linear page memory address calculation