F100K
Abstract: SY100S341
Text: T0013fll « 0002213 3Û0 8-BIT SHIFT REGISTER SYNERGY SY100S341 S E M IC O N D U C T O R FEATURES • ■ Max. shift frequency of 600MHz ■ Max. Clock to Q delay of 1200ps ■ Iee min. of -150m A ■ ESD protection of 2000V ■ Industry standard 100K ECL levels
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T0013fll
SY100S341
600MHz
1200ps
-150mA
F100K
SY100S341
D24-1
F100K
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Untitled
Abstract: No abstract text available
Text: SY100S366 9-BIT COMPARATOR SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION • Max. propagation delay of I500ps ■ le e min. of-120mA ■ ESD protection of 2000V ■ Industry standard 100K ECL levels ■ Extended supply voltage option: — VEE = -4.2V to -5.46V
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SY100S366
I500ps
of-120mA
75Ki2
F100K
SY100S366DC
D24-1
SY100S366FC
F24-1
SY100S366JC
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Untitled
Abstract: No abstract text available
Text: V PRELIMINARY SY10ELT22L SY100ELT22L d u a l t t l -t o - d if f e r e n t ia l SYNERGY p e c l tr a n s la to r SEMICONDUCTOR DESCRIPTION FEATURES The SY10ELT/100ELT22L are dual TTL-to-differential PECL translators. Because PECL Positive ECL levels are used, only +3.3V and ground are required. The small
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SY10ELT22L
SY100ELT22L
SY10ELT/100ELT22L
ELT22L
10ELT
100ELT
300ps
100ps
Super-300K
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Untitled
Abstract: No abstract text available
Text: * 12-BIT PARITY GENERATOR/CHECKER SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION • ■ ■ ■ ■ ■ ■ ■ Provides odd-HIGH parity of 12 Inputs Output register with Shift/Hold capability 900ps max. D to Q/Q output Enable control Asynchronous Register Reset
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12-BIT
SY10E160
SY100E160
900ps
MC10E/100E160
SY10E160
SY100E160
12-bit
SY10E160JC
J28-1
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Untitled
Abstract: No abstract text available
Text: ^ e v u m r v S IN G L E s S S S Ê Ê S F S U P P L Y 1:4C L0C K D R IV ER p r e l i m i n a r y svittiooH 843 DESCRIPTION FEATURES • Translates positive ECL to TTL PECL-TTL ■ 300ps pln-to-pin skew ■ Guaranteed skew spec ■ Differential internal design for increased noise
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300ps
SY10H843
SY100H843
SY10/100H843
SY10H843ZC
Z16-1
SY100H843ZC
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Untitled
Abstract: No abstract text available
Text: * 5-BIT 2:1 MULTIPLEXER SYNERGY SY10E158 SY100E158 SEMICONDUCTOR FEATURES DESCRIPTION • ■ ■ ■ ■ 550ps max. D to output 775ps max. SEL to output Differential outputs ESD protection of 2000V Fully compatible with industry standard 10KH, 100K ECL levels
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SY10E158
SY100E158
550ps
775ps
MC10E/100E158
SY10E158
SY100
SY10E158JC
J28-1
SY100E158JC
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DG7-32
Abstract: No abstract text available
Text: * SYNERGY DATA S E P A R A TO R PRELIMINARY SY10E197 SEMICONDUCTOR FEATURES • ■ ■ ■ ■ ■ 2:7 and 1:7 RLL format-compatible Fully Integrated Vco for 50Mb/s operation External Vco input for higher operating frequency Anti-equivocation circuitry to ensure PLL lock
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SY10E197
50Mb/s
MC10E197
SY10E197
50Mb/s,
DG732
DG7-32
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ET 8211
Abstract: tvccd 20 band equalizer twisted pair cable with parameter
Text: »es* SYNERGY A STS'3 ADAPT,VE EQUALIZER P R E L 'sY 6 7 6 7 2 SEMICONDUCTOR FEATURES DESCRIPTION • Adaptive Equalizer with Line Compensation Loop Control ■ Compiles with ATM Forum STS-3 Twisted Pair Specifications ■ Transmitter output disable option for quiet line
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32-pin
ML6672
100BASE-TX)
SY67672
SY67672
10jiF
SY67672CQ
SY67672CH
ET 8211
tvccd
20 band equalizer
twisted pair cable with parameter
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Untitled
Abstract: No abstract text available
Text: * QUAD MULTIPLEXER/ LATCH SYNERGY SEMICONDUCTOR FEATURES SY100S355 DESCRIPTION • Max. propagation delay of 1100ps ■ Max. enable to output delay of I400ps ■ I ee min. of -80m A ■ ESD protection of 2000V ■ Industry standard 100K ECL levels ■ Extended supply voltage option:
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SY100S355
1100ps
I400ps
F100K
SY100S355DC
D24-1
SY100S3S5FC
F24-1
SY100S355JC
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Untitled
Abstract: No abstract text available
Text: A LOW-POWER OCTAL ECL/TTL SYNERGY S SEMICONDUCTOR — W l IH L A I O n “ " I DESCRIPTION FEATURES • Bi-directional translation ■ ESD protection of 2000V ■ Latched outputs ■ Voltage compensated operating range: -4.2V to -5.7V ■ Fast TTL outputs
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F100K
SY100S328
SY100S328
SY100S282DC
D24-1
SY100S328FC
F24-1
SY100S328JC
J28-1
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Untitled
Abstract: No abstract text available
Text: * SYNERGY 2K X 9 ADVANCED SELF-TIMED SRAM SEMICONDUCTOR FEATURES • Extremely fast access times: tcHCH = 5/6ns max. ■ Extended supply voltage option: — Vee = -5.2V ■ Completely self-timed read and write cycle ■ On-chip input and output registers
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-400mA
-350mA
SY101492-5
SY101492-6
SY101492
SY101492-5ECF
E64-1
SY101492-6ECF
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Untitled
Abstract: No abstract text available
Text: * SINGLE SUPPLY PECL-TTL 1:9 CLOCK DRIVER SYNERGY SEMICONDUCTOR Clockworks PRELIMINARY SY10/100H641 DESCRIPTION FEATURES • PECL-TTL version of popular ECLinPS E111 ■ Guaranteed low skew specification ■ Latch ■ Differential internal design ■ V bb output for single-ended operation
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SY10/100H641
10Hxxx)
MC10H641/100H641
SY10H641
SY100H641
28-lead
SY10H641JC
J28-1
SY100H641JC
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DALE crystal 16Mhz
Abstract: SY89429A SY89429AJC
Text: * Clockworks PRELIMINARY SY89429A FREQUENCY SYNTHESIZER SYNERGY SEMICONDUCTOR DESCRIPTION FEATURES • ■ ■ ■ ■ ■ ■ 25 to 400MHz differential PECL outputs 10ps rms max. jitter Minimal frequency over-shoot Synthesized architecture Serial 3 wire interface
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SY89429A
400MHz
SY89429A
800MHz.
S0Q13Ã
SY89429AJC
J28-1
SY89429A2C
Z28-1
DALE crystal 16Mhz
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SY100H841ZC
Abstract: SY10H841ZC
Text: This Material Copyrighted By Its Respective Manufacturer This Material Copyrighted By Its Respective Manufacturer Clockworks PRELIMINARY SY10/100H841 SYNERGY S EM IC O N D U C TO R AC CHARACTERISTICS VT = VE = 5.0 V ± 5% T a = +25°C T a = 0°C T a = +85°C
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SY10/100H641
0000b07
SY10H841ZC
Z16-1
SY100H841ZC
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Untitled
Abstract: No abstract text available
Text: * SY10494-6/7 SY100494-6/7 SY101494-6/7 16K x 4 ECL RAM SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION • Address access time, tAA: 6/7ns max. The Synergy S Y 1 0 /1 0 0 /1 0 1 4 9 4 are 65536-bit Random Access Memories RA M s , designed with advanced Emitter
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SY10494-6/7
SY100494-6/7
SY101494-6/7
65536-bit
16384-words-by-4-bits
10K/100K
SY100494-6CCF
SY100494-6FCF
SY100494-7CCF
SY100494-7FCF
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Untitled
Abstract: No abstract text available
Text: uIPL SYNERGY SEMICONDUCTOR PRELIMINARY TTL BICMOS STATIC RAM 64K 16KX 4-BIT V 1 FEATURES SY71B98-7 SY71B98-10 SY71B98-12 DESCRIPTION • ■ ■ ■ ■ Address access time, tA A : 7/10/12ns max. Chip select access time, tACS: 4/6/7ns max. Popular 16K x 4 with common I/O organization
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SY71B98-7
SY71B98-10
SY71B98-12
7/10/12ns
200mA
24-pln,
300-mil
SY71B98
536-bit
T0013fll
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Untitled
Abstract: No abstract text available
Text: * SYNERGY QUAD DRIVER SY10E112 SY100E112 SEMICONDUCTOR FEATURES DESCRIPTION • 600ps max. propagation delay ■ Common enable input ■ ESD protection of 2000V ■ Fully compatible with Industry standard 10KH, 100 K I/O levels ■ Extended 100E V ee range of -4.2V to -5.46V
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SY10E112
SY100E112
600ps
75Ki2
MC10E/100E112
SY10E112
SY100E112
ske75
SY10E112JC
J28-1
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Untitled
Abstract: No abstract text available
Text: « SYNERGY C lockw orks PRELIMINARY FREQUENCY SYNTHESIZER SY89429 SEMICONDUCTOR DESCRIPTION FEATU R ES The SY89429 is a general purpose, synthesized clock source targeting applications that require both serial and parallel interfaces. Its Internal V co will operate over a range
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SY89429
SY89429
800MHz.
16MHz
400MHz
T0D13Ã
SY89429JC
J28-1
DD13fll
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Untitled
Abstract: No abstract text available
Text: * Clockworks PRELIMINARY SY89429A FREQUENCY SYNTHESIZER SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION • 25 to 400MHz differential PECL outputs ■ ■ ■ ■ ■ ■ 10ps rms max. jitter Minimal frequency over-shoot Synthesized architecture Serial 3 wire interface
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SY89429A
400MHz
SY89429A
S0G13Ã
SY89429AJC
SY89429AZC
J28-1
Z28-1
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Untitled
Abstract: No abstract text available
Text: * LOW-POWER HEX ECL-to-TTL TRANSLATOR SYNERGY SY100S325 SEMICONDUCTOR DESCRIPTION FEATURES The SY100S325 are hex translators for converting 100K ECL logic levels to TTL logic levels. Inputs can be used as inverting, non-inverting o r differential receivers. An
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SY100S325
SY100S325
SY100S325DC
D24-1
SY100S325FC
F24-1
SY100S325JC
J28-1
000102B
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F100K
Abstract: SY100S336 SY100S336A SY100S336ADC
Text: ENHANCED 4-STAGE COUNTER/SHIFT REGISTER m v SYNERGY . Vim <N «4 S i i 00S336A S E M IC O N D U C T O R DESCRIPTION FEATURES • Max. shift frequency of 700MHz ■ Clock to Q delay max. of 110Ops ■ Sn to TC speed improved by 50% ■ Sn set-up and hold time reduced by more than 50%
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SY100S336A
700MHz
110Ops
-170mA
F100K
SY100S336A
TD013Ã
SY100S336ADC
D24-1
F100K
SY100S336
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F100K
Abstract: SY100S350 SY100S350DC
Text: « SYNERGY H E X D' LATCH SY100S350 S E M IC O N D U C T O R FEATURES DESCRIPTION I Max. transparent propagation delay of 900ps I Min. Master Reset and Enable pulse widths of 100ps I I e e min. of -98mA I ESD protection of 2000V I Industry standard 100K ECL levels
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SY100S350
900ps
100ps
-98mA
F100K
SY100S350
SY100S350DC
D24-1
SY10OS35OFC
F100K
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31T4
Abstract: No abstract text available
Text: DS3/STS-1 CLOCK fr._. RECOVERING TRANSCEIVER O V A IC P O V S Y N cH G Y PRELIMINARY INFORMATION SEMICONDUCTOR DESCRIPTION FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Single-chlp line Interface for DS3 and STS-1 Transformers optional for connection to 75ft coax
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30-300mV)
100-pin
14x20
SY67731
T0013fll
31T4
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Untitled
Abstract: No abstract text available
Text: * TRIPLE D FLIP-FLOP SYNERGY SY100S331 SEMICONDUCTOR FEATURES DESCRIPTION • Max. toggle frequency of 800MHz ■ Differential outputs ■ I e e min. of -80m A ■ ESD protection of 2000V ■ Industry standard 100K ECL levels ■ Extended supply voltage option:
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SY100S331
800MHz
SY100S331
SY100S331DC
D24-1
SY100S331FC
F24-1
SY100S331JC
J28-1
SY100S331JCTR
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