MIPS64
Abstract: "network interface cards"
Text: RM9120 Preliminary FEATURES AM RM9120 Integrated Microprocessor NETWORKING INTERFACES • A CPU core compatible with the MIPS64 Instruction Set Architecture. • High-speed integrated DDR SDRAM, SysAD, Local Bus, HyperTransport, and Ethernet MAC interfaces. Option
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RM9120
RM9120
MIPS64TM
672-pin
PMC-2031705
MIPS64
"network interface cards"
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L2 cache L3 cache
Abstract: RM7000 GT-64120A IEEE754 RM7000A mips uart
Text: RM7000A 125 MHz max. freq., multiplexed address/data bus SysAD • Supports two outstanding reads with out-of-order return High-performance floating-point unit • 800 MFLOPS maximum • IEEE754 compliant single and double precision floating-point operations
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RM7000A
IEEE754
64-bit
interrupts-10
64-Bit
100MHz
RM7000A
L2 cache L3 cache
RM7000
GT-64120A
mips uart
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GT-64120A
Abstract: EV-64120A-7000 IEEE754 RM7000 RM7000B 64120A
Text: RM7000B Preliminary 64-Bit MIPS RISC Microprocessor with Integrated L2 Cache FEATURES 125 MHz max. freq., multiplexed address/data bus SysAD • Supports two outstanding reads with out-of-order return High-performance floating-point unit • 1000 MFLOPS maximum
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RM7000B
64-Bit
IEEE754
32bit
RM7000B
GT-64120A
EV-64120A-7000
RM7000
64120A
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ARXD 149
Abstract: PAD015 U2554 PAD130 PAD031 PAD115 C113 C114 C126 C127
Text: A B C D E RST_control SERclk BYPASS QUICK SWITCH SysAD[0.63] SysADC[0.7] SysAD[0.63] SysADC[0.7] AD[0.63] ADP[0.7] BypsOe 4 AD[0.63] ADP[0.7] BypsOe 4 {Value} DEVICE BUFFER & LATCH {Value} {Value} DEVICE SERint FlashRST* RST_control {Value} CPU-RST-PAL
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EVB64120
74FCT163244
48-TSS0P
ARXD 149
PAD015
U2554
PAD130
PAD031
PAD115
C113
C114
C126
C127
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RM5200
Abstract: API NETWORKS Marvell MIPS64 RM7000 RM9200 E9000
Text: RM9200 Released RM9200 Integrated Multiprocessor FEATURES • 10 Watts typical power consumption. • High speed integrated DDR SDRAM, HyperTransport, SysAD and local bus interfaces. The RM9200 Integrated Multiprocessor is PMC-Sierra's next generation high
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RM9200
RM9200
RM7000
RM5200
E9000
16-Kbyte,
256-Kbyte,
PMC-2011766
API NETWORKS
Marvell
MIPS64
RM7000
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GT-64120A
Abstract: IEEE754 RM7000 RM7000A
Text: RM7000A Preliminary 64-Bit MIPS RISC Microprocessor with Integrated L2 Cache FEATURES 125 MHz max. freq., multiplexed address/data bus SysAD • Supports two outstanding reads with out-of-order return High-performance floating-point unit • 800 MFLOPS maximum
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RM7000A
64-Bit
IEEE754
interrupts-10
RM7000A
GT-64120A
RM7000
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ARXD 149
Abstract: RDATA34 programming 29F400 C100 C101 C102 C103 C104 C105 C106
Text: A B C D E RST_control SERclk BYPASS QUICK SWITCH SysAD[0.63] SysADC[0.7] SysAD[0.63] SysADC[0.7] AD[0.63] ADP[0.7] BypsOe 4 AD[0.63] ADP[0.7] BypsOe 4 {Value} DEVICE BUFFER & LATCH {Value} {Value} DEVICE SERint FlashRST* RST_control {Value} CPU-RST-PAL
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EVB64120
74FCT163244
48-TSS0P
ARXD 149
RDATA34
programming 29F400
C100
C101
C102
C103
C104
C105
C106
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Untitled
Abstract: No abstract text available
Text: Product Brief TMPR4951BFG–200 TX4951B 64-Bit RISC Processor Highlights Description • 32-bit SysAD bus support The TX4951B is a 64-bit RISC (Reduced Instruction Set Computer) microprocessor that is a low-cost, low-power microprocessor developed for interactive
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TMPR4951BFGâ
TX4951B)
64-Bit
32-bit
TX4951B
100-pin
TMPR4955BF
TX49/L3
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NEC BONITO
Abstract: diode t25 4 F6 VR43xx dba1 VR5432 VR5500 NEC AC12 SCBE 2 AD11 PC-100
Text: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD65949S1-P00-F6 BONITOTM - Companion Chip for VR43xx and VR5xxx DESCRIPTION ‘Bonito’ is a system controller especially designed for MIPS RISC microprocessors with a 32-bit SysAD bus. ‘Bonito’ incorporates a simple and fast memory interface for PC-100 compliant SDRAMs, a Rev 2.1 compliant
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PD65949S1-P00-F6
VR43xx
32-bit
PC-100
Hz/32-bit
16-bit
VR43xx,
VR5432
VR5500
NEC BONITO
diode t25 4 F6
dba1
NEC AC12
SCBE 2
AD11
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RM7000
Abstract: marvell ethernet switch GT-64120A IEEE754 RM7000A
Text: RM7000A 64-Bit MIPS RISC Microprocessor with Integrated L2 Cache FEATURES 125 MHz max. freq., multiplexed address/data bus SysAD • Supports two outstanding reads with out-of-order return High-performance floating-point unit • 800 MFLOPS maximum • IEEE754 compliant single and
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RM7000A
64-Bit
IEEE754
interrupts-10
32bit
RM7000A
RM7000
marvell ethernet switch
GT-64120A
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RM7000C
Abstract: RM7000 600MHz RM7000 GT-6424 IEEE754
Text: RM7000C Preliminary 64-Bit MIPS RISC Microprocessor with Integrated L2 Cache FEATURES 1600 Mbyte per-second peak throughput • 200 MHz max. freq., HSTL multiplexed address/data bus SysAD200 • Supports two outstanding reads with out-of-order return High-performance floating-point unit
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RM7000C
64-Bit
SysAD200)
IEEE754
32bit
RM7000C
RM7000 600MHz
RM7000
GT-6424
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how to use timer in bascom
Abstract: ali 3511 NKK DATE code 1304h NR4650 NKK NR4650
Text: Preliminary ND5000LBG ND5000LBG System Controller with PCI Bus for NR5XXX /NR4700 /NR46XX CPUs Preliminary Rev.4.0 Oct. 1998 SYSTEM BLOCK DIAGRAM < CPU > / / / / NR46 00 NR46 50 NR47 00 NR50 00 NR56 50 < DRAM > Memory bus 3.3V SysAD bus (3.3V) SDR A M EDO
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ND5000LBG
/NR4700
/NR46XX
00LBG
ND5000LBG
0-70C
0-70C.
how to use timer in bascom
ali 3511
NKK DATE code
1304h
NR4650
NKK NR4650
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32 pin eprom to eprom copier circuit
Abstract: VR5432 NEC VR4310 NEC BONITO VR4310 MIPS R4X00 sdram PC-100 VR4305 NEC disk controller SO-DIMM 100-pin
Text: Bonito VR family System Controller for MIPS CPUs Product Letter Description The ‘Bonito’ is a system controller especially designed for MIPS RISC microprocessors with a 32-bit SysAD bus. ‘Bonito’ incorporates a simple and fast memory interface for PC-100 compliant
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32-bit
PC-100
Hz/32-bit
16-bit
32-bit
VR43xx
VR5432
352-pin
32 pin eprom to eprom copier circuit
NEC VR4310
NEC BONITO
VR4310
MIPS R4X00 sdram
VR4305
NEC disk controller
SO-DIMM 100-pin
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R3051
Abstract: R4650 R4700 TN-26 64-Bit Microprocessors
Text: ORION SYSAD OUTPUT TIMING ISSUES TECHNICAL NOTE TN-26 Integrated Device Technology, Inc. by Robert Napaa INTRODUCTION The IDT Orion™ Family of 64-bit microprocessors supports a wide variety of processor-based applications, including 32bit Windows NT desktop or notebook systems and embedded
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TN-26
64-bit
32bit
R4600,
R4700,
R4650.
R4600/R4700)
R4650)
R3051
R4650
R4700
TN-26
64-Bit Microprocessors
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Untitled
Abstract: No abstract text available
Text: RM9120 Preliminary FEATURES AM RM9120 Integrated Microprocessor NETWORKING INTERFACES • A CPU core compatible with the MIPS64 Instruction Set Architecture. • High-speed integrated DDR SDRAM, SysAD, Local Bus, HyperTransport, and Ethernet MAC interfaces. Option
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RM9120
RM9120
MIPS64â
672-pin
PMC-2031705
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Untitled
Abstract: No abstract text available
Text: Product Brief TMPR4951BFG–200 TX4951B 64-Bit RISC Processor Highlights Description • 32-bit SysAD bus support The TX4951B is a 64-bit RISC (Reduced Instruction Set Computer) microprocessor that is a low-cost, low-power microprocessor developed for interactive
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TMPR4951BFGâ
TX4951B)
64-Bit
32-bit
TX4951B
100-pin
TMPR4955BF
TX49/L3
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TMPR4955BFG/CFG
Abstract: No abstract text available
Text: Product Brief TMPR4955BFG/CFG, TMPR4956CXBG TX4955/TX4956 64-Bit RISC Processor Highlights Description • SysAD bus support The TX4955/TX4956 is a 64-bit RISC (Reduced Instruction Set Computer) microprocessor that is a low-cost, lowpower microprocessor developed for
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TMPR4955BFG/CFG,
TMPR4956CXBG
TX4955/TX4956)
64-Bit
TX49/H3
TX49/H4
32-bit
TX4955)
64-bit/32-bit
TMPR4955BFG/CFG
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GT-64120A
Abstract: RM7000 RM7000B IEEE754
Text: RM7000B Preliminary 64-Bit MIPS RISC Microprocessor with Integrated L2 Cache FEATURES 125 MHz max. freq., multiplexed address/data bus SysAD • Supports two outstanding reads with out-of-order return High-performance floating-point unit • 1000 MFLOPS maximum
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RM7000B
64-Bit
IEEE754
RM7000B
GT-64120A
RM7000
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SR71010A
Abstract: L2 cache L3 cache MIPS64 ieee intelligent image processing line-locked SR7101 SR71010 MIPS64 instruction set
Text: SR71010A TM MIPS64 SUPERSCALAR MICROPROCESSOR ENGINES FOR THE DIGITAL AGE TM TM The SR71010A is a true 2-way superscalar MIPS64 PC gen iTLB BHT buffer i-cache decode BRU register file FP reg file dispatch dispatch ALUx ALUy LD/ST MOV LOAD SysAD & L3 Interface
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SR71010A
MIPS64
SR71010A
MIPS64
600MHz,
MIPS64TM
L2 cache L3 cache
ieee intelligent image processing
line-locked
SR7101
SR71010
MIPS64 instruction set
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Untitled
Abstract: No abstract text available
Text: System Interface Protocols Chapter 11 Introduction The following sections contain a cycle-by-cycle description of the system interface protocols for each type of R5000 processor and external request. Address and Data Cycles Cycles in which the SysAD bus contains a valid address are called
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R5000
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divmode
Abstract: No abstract text available
Text: NEC 1. ¿¿PD30200, 30210 PIN FUNCTIONS Pin Name I/O SysAD 31:0 I/O Function System address/data bus. 32-bit bus for communication between processor and external agent. SysCmd (4:0) I/O System command/data ID bus. 5-bit bus for communication of commands and data identifiers between processor
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uPD30200
uPD30210
32-bit
divmode
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Untitled
Abstract: No abstract text available
Text: ¿¿PD30111 NEC 5. BCU BUS CONTROL UNIT The BCU transfers data with the V r41 10 CPU core via SysAD bus (internal) inside the V r41 11. It also controls an external LCD controller, DRAM, ROM (flash memory or mask ROM), and PCMCIA controller via system bus, and
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uPD30111
Vr4111
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Untitled
Abstract: No abstract text available
Text: System Interface Protocols Chapter 11 Introduction The following sections contain a cycle-by-cycle description of the system interface protocols for each type of R5000 processor and external request. Address and Data Cycles Cycles in w hich the SysAD bu s contains a valid address are called
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R5000
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TMPR4951F
Abstract: No abstract text available
Text: TO SHIBA TMPR4951F TOSHIBA RISC PROCESSOR TENTATIVE TMPR4951F 64-bit RISC MICROPROCESSOR 1. GENERAL DESCRIPTION The TMPR4951F is a 64-bit RISC (Reduced Instruction Set Computer) microprocessor that is a lowcost, low-power microprocessor developed for interactive consumer applications including LBP,
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TMPR4951F
64-bit
TMPR4951F
32-bit
16-Kbyte
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