SYMBOL MC100 Search Results

DL140

Abstract: MC100E256 MC10E256
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3ĆBit 4:1 MuxĆLatch MC10E256 MC100E256 The MC10E/100E256 contains three 4:1 multiplexers followed by transparent latches with differential outputs. Separate Select controls are provided for the leading 2:1 mux pairs see logic symbol .

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Error Detection/Correction Circuit MC10E193 MC100E193 The MC10E/100E193 is an error detection and correction EDAC circuit. Modified Hamming parity codes are generated on an 8-bit word according to the pattern shown in the logic symbol. The P5 output gives

DL140

Abstract: E160 MC100E193 MC10E193
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Error Detection/Correction MC10E193 Circuit MC100E193 The MC10E/100E193 is an error detection and correction EDAC circuit. Modified Hamming parity codes are generated on an 8-bit word according to the pattern shown in the logic symbol. The P5 output gives

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Error Detection/Correction Circuit MC10E193 MC100E193 The MC10E/100E193 is an error detection and correction EDAC circuit. Modified Hamming parity codes are generated on an 8-bit word according to the pattern shown in the logic symbol. The P5 output gives

Motorola, Inc. identical in pinout to

Abstract: DL140 MC100E171 MC10E171
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3ĆBit 4:1 Multiplexer MC10E171 MC100E171 The MC10E/100E171 contains three 4:1 multiplexers with differential outputs. Separate Select controls are provided for the leading 2:1 mux pairs see logic symbol . The three Select inputs control which one of the

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Error Detection/Correction Circuit MC10E193 MC100E193 The MC10E/100E193 is an error detection and correction EDAC circuit. Modified Hamming parity codes are generated on an 8-bit word according to the pattern shown in the logic symbol. The P5 output gives the parity of the

AN1404

Abstract: AN1405 AND8020 MC100E256 MC100E256FN MC100E256FNR2 D2D marking code
Contextual Info: MC100E256 5VĄECL 3ĆBit 4:1 MuxĆLatch The MC100E256 contains three 4:1 multiplexers followed by transparent latches with differential outputs. Separate Select controls are provided for the leading 2:1 mux pairs see logic symbol . When the Latch Enable (LEN) is LOW, the latch is transparent, and

marking CODE D2B

Abstract: ic 4050 pin diagram
Contextual Info: MC100E256 5V ECL 3-Bit 4:1 Mux-Latch The MC100E256 contains three 4:1 multiplexers followed by transparent latches with differential outputs. Separate Select controls are provided for the leading 2:1 mux pairs see logic symbol . When the Latch Enable (LEN) is LOW, the latch is transparent, and

AN1404

Abstract: AN1405 AND8020 MC100E256 MC100E256FN MC100E256FNR2
Contextual Info: MC100E256 5V ECL 3-Bit 4:1 Mux-Latch The MC100E256 contains three 4:1 multiplexers followed by transparent latches with differential outputs. Separate Select controls are provided for the leading 2:1 mux pairs see logic symbol . When the Latch Enable (LEN) is LOW, the latch is transparent, and

3525 "application note"

Abstract: SECDED ic 4050 AN1404 AND8020 E160 MC100E193 MC100E193FN MC100E193FNR2 socket 775 pinout
Contextual Info: MC100E193 5VĄECL Error Detection/ Correction Circuit The MC100E193 is an error detection and correction EDAC circuit. Modified Hamming parity codes are generated on an 8-bit word according to the pattern shown in the logic symbol. The P5 output gives the parity of the whole word. The word parity is also

Contextual Info: MC10E256, MC100E256 5VĄECL 3ĆBit 4:1 MuxĆLatch The MC10E/100E256 contains three 4:1 multiplexers followed by transparent latches with differential outputs. Separate Select controls are provided for the leading 2:1 mux pairs see logic symbol . When the Latch Enable (LEN) is LOW, the latch is transparent, and

socket 775 pinout

Abstract: PLCC28 package
Contextual Info: MC100E193 5V ECL Error Detection/ Correction Circuit The MC100E193 is an error detection and correction EDAC circuit. Modified Hamming parity codes are generated on an 8-bit word according to the pattern shown in the logic symbol. The P5 output gives the parity of the whole word. The word parity is also

MC100E171

Abstract: MC100E171FN MC100E171FNR2 MC10E171 MC10E171FN MC10E171FNR2 D1C marking
Contextual Info: MC10E171, MC100E171 5VĄECL 3ĆBit 4:1 Multiplexer The MC10E/100E171 contains three 4:1 multiplexers with differential outputs. Separate Select controls are provided for the leading 2:1 mux pairs see logic symbol . The three Select inputs control which one of the four data inputs in each case is propagated to

MC100E256

Abstract: MC100E256FN MC100E256FNR2 MC10E256 MC10E256FN MC10E256FNR2
Contextual Info: MC10E256, MC100E256 5VĄECL 3ĆBit 4:1 MuxĆLatch The MC10E/100E256 contains three 4:1 multiplexers followed by transparent latches with differential outputs. Separate Select controls are provided for the leading 2:1 mux pairs see logic symbol . When the Latch Enable (LEN) is LOW, the latch is transparent, and

Contextual Info: MC100E193 5V ECL Error Detection/ Correction Circuit The MC100E193 is an error detection and correction EDAC circuit. Modified Hamming parity codes are generated on an 8-bit word according to the pattern shown in the logic symbol. The P5 output gives the parity of the whole word. The word parity is also

Contextual Info: MC10E171, MC100E171 5V ECL 3-Bit 4:1 Multiplexer The MC10E/100E171 contains three 4:1 multiplexers with differential outputs. Separate Select controls are provided for the leading 2:1 MUX pairs see logic symbol . The three Select inputs control which one of the four data inputs in each case is propagated to

Marking D1c

Abstract: MC100E171 MC100E171FN MC100E171FNR2 MC10E171 MC10E171FN MC10E171FNR2
Contextual Info: MC10E171, MC100E171 5V ECL 3-Bit 4:1 Multiplexer The MC10E/100E171 contains three 4:1 multiplexers with differential outputs. Separate Select controls are provided for the leading 2:1 MUX pairs see logic symbol . The three Select inputs control which one of the four data inputs in each case is propagated to

MARKING d2b

Abstract: Marking D1c MC100E171 MC10E171 MC10E171FN
Contextual Info: MC10E171, MC100E171 5V ECL 3-Bit 4:1 Multiplexer Description The MC10E/100E171 contains three 4:1 multiplexers with differential outputs. Separate Select controls are provided for the leading 2:1 MUX pairs see logic symbol . The three Select inputs control which one of the four data inputs in each case is propagated to

MC100E171

Abstract: MC10E171 MC10E171FN
Contextual Info: MC10E171, MC100E171 5V ECL 3-Bit 4:1 Multiplexer Description The MC10E/100E171 contains three 4:1 multiplexers with differential outputs. Separate Select controls are provided for the leading 2:1 MUX pairs see logic symbol . The three Select inputs control which one of the four data inputs in each case is propagated to

"on semiconductor"

Abstract: E160 MC100E193 MC100E193FN MC100E193FNR2 MC10E193 MC10E193FN MC10E193FNR2 p4350
Contextual Info: MC10E193, MC100E193 5VĄECL Error Detection/ Correction Circuit The MC10E/100E193 is an error detection and correction EDAC circuit. Modified Hamming parity codes are generated on an 8-bit word according to the pattern shown in the logic symbol. The P5 output gives the parity of the whole word. The word parity is also

Contextual Info: MC10E171, MC100E171 5V ECL 3-Bit 4:1 Multiplexer Description The MC10E/100E171 contains three 4:1 multiplexers with differential outputs. Separate Select controls are provided for the leading 2:1 MUX pairs see logic symbol . The three Select inputs control which one of the four data inputs in each case is propagated to

qo-10

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3-Bit 4:1 M ultiplexer The MC10E/100E171 contains three 4:1 m ultiplexers with differential outputs. Separate Select controls are provided for the leading 2:1 mux pairs see logic symbol . The three Select inputs control w hich one of the

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3-Bit 4:1 Mux-Latch M C10E256 M C100E256 The M C 10E/100E256 contains three 4:1 m ultiplexers follow ed by transparent latches with differential outputs. Separate Select controls are provided for the leading 2:1 m ux pairs see logic symbol .

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Error Detection/C orrection Circuit M C10E193 M C 100E193 The MC10E/100E193 is an error detection and correction EDAC circuit. Modified Hamming parity codes are generated on an 8-bit word according to the pattern shown in the logic symbol. The P5 output gives