SY100S360JC Search Results

ZB500

Abstract: "Parity Checker" application of parity checker/generator F100K SY100S360 SY100S360FC SY100S360JC SY100S360JCTR
Contextual Info: DUAL PARITY CHECKER/ GENERATOR FEATURES I1a I0a I2a I4a I3a VEES PIN CONFIGURATIONS I5a 11 10 9 8 7 6 5 I6a I7a VEE VEES I0b BLOCK DIAGRAM I0a I1a I2b Za Top View PLCC J28-1 Ia Za VCCA VCC VCC C Zb I6a I7a I5a I4b I5b I6b 2 3 17 16 I4a I3a 15 14 I2a I1a 13

"Parity Checker"

Abstract: F100K SY100S360 SY100S360DC SY100S360FC D0G22 ha13
Contextual Info: * DUAL PARITY CHECKER/GENERATOR SYNERGY S E M IC O N D U C T O R FEATURES SY100S360 DESCRIPTION • Max. propagation delay of 2200ps I e e min. of -70mA ■ ■ ESD protection of 2000V ■ Industry standard 100K ECL levels ■ Extended supply voltage option:

"Parity Checker"

Abstract: F100K SY100S360 SY100S360DC SY100S360FC
Contextual Info: « DUAL PARITY CHECKER/GENERATOR SYNERGY SEMICONDUCTOR FEATURES SY100S360 D E S C R IP T IO N • Max. propagation delay of 2200ps ■ I ee min. of -70mA ■ ESD protection of 2000V ■ Industry standard 100K ECL levels ■ Extended supply voltage option:

F100K

Abstract: SY100S360 SY100S360FC SY100S360FCTR SY100S360JC SY100S360JCTR Marking ZB
Contextual Info: Micrel, Inc. DUAL PARITY CHECKER/ GENERATOR FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ SY100S360 SY100S360 DESCRIPTION The SY100S360 is a dual parity checker/generator and is designed for use in high-performance ECL systems. The inputs are segmented into two groups of nine inputs each

Contextual Info: * SYNERGY SEMICONDUCTOR DUAL PARITY CHECKER/GENERATOR FEATURES SY100S360 DESCRIPTION The SY100S360 is a dual parity checker/generator and is designed for use in high-performance ECL systems. The inputs are segmented into two groups of nine inputs each and the parity output is at a logic LOW when an even

F100K

Abstract: SY100S360 SY100S360FC SY100S360JC SY100S360JCTR
Contextual Info: DUAL PARITY CHECKER/ GENERATOR FEATURES I1a I0a I2a I4a I3a VEES PIN CONFIGURATIONS I5a 11 10 9 8 7 6 5 I6a I7a VEE VEES I0b BLOCK DIAGRAM I0a I1a I2b Za Top View PLCC J28-1 Ia Za VCCA VCC VCC C Zb I6a I7a I5a I4b I5b I6b 2 3 17 16 I4a I3a 15 14 I2a I1a 13

Contextual Info: « DUAL PARITY CHECKER/GENERATOR SYNERGY SEMICONDUCTOR FEATURES SY100S360 DESCRIPTION • Max. propagation delay of 2200ps ■ Iee mln. of -70mA ■ ESD protection of 2000V ■ Industry standard 100K ECL levels ■ Extended supply voltage option: — VEE = -4.2V to -5.46V

application of parity checker/generator

Abstract: F100K SY100S360 SY100S360JC SY100S360JCTR
Contextual Info: Micrel, Inc. DUAL PARITY CHECKER/ GENERATOR FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ SY100S360 SY100S360 DESCRIPTION The SY100S360 is a dual parity checker/generator and is designed for use in high-performance ECL systems. The inputs are segmented into two groups of nine inputs each

Contextual Info: * SYNERGY DUAL PARITY CH ECKER /G EN ERATO R SY100S360 SEMICONDUCTOR FEATURES DESCRIPTION Max. propagation delay of 2200ps Iee min. o f-70 m A Industry standard 100K ECL levels Extended supply voltage option: V ee = -4.2V to -5.5V Voltage and temperature compensation for

Contextual Info: * DUAL PARITY CHECKER/GENERATOR SYNERGY SY100S360 SEMICONDUCTOR FEATURES DESCRIPTION Max. propagation delay of 2200ps min. o f-7 0m A Industry standard 100K ECL levels Iee Extended supply voltage option: V ee = -4 .2V to -5.5V Voltage and temperature compensation for

Contextual Info: * DUAL PARITY CHECKER/GENERATOR SYNERGY SEMICONDUCTOR FEATURES SY100S360 DESCRIPTION • Max. propagation delay of 2200ps ■ Iee min. of -70mA ■ ESD protection of 2000V ■ Industry standard 100K ECL levels ■ Extended supply voltage option: V ee = -4.2V to -5.5V

1913B

Contextual Info: n i j a I. SYNERGY pa m i y HFf'KF'R/i’f NFjflMi ='''<»«60 3 E M ¡C O N D U C I O h D ES C R IPTIO N • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Max. propagation delay of 2200ps Iee min. of -70mA Industry standard 100K ECL levels Extended supply voltage option: