SY100S3 Search Results

LD 757 ps

Contextual Info: * LOW POW ER HEX TTL-to-ECL TRANSLATO R SYNERGY SY100S324 S E M IC O N D U C T O R DESCRIPTION FEATURES Max. propagation delay of 1.4ns The SY100S324 is a hex translator designed to convert T T L logic levels to 100K ECL levels. The inputs are TTL com patible with diffe re n tia l o utputs that can e ith e r be

F100K

Abstract: SY100S304 SY100S304FC SY100S304JC SY100S304JCTR
Contextual Info: QUINT AND/NAND GATE FEATURES SY100S304 DESCRIPTION • Max. propagation delay of 1050ps ■ IEE min. of –60mA ■ Extended supply voltage option: VEE = –4.2V to –5.5V ■ Voltage and temperature compensation for improved noise immunity ■ Internal 75KΩ input pull-down resistors

F100K

Abstract: SY100S301 SY100S301FC SY100S301JC SY100S301JCTR F100K ECL book
Contextual Info: TRIPLE 5-INPUT OR/NOR GATE SY100S301 DESCRIPTION FEATURES • Max. propagation delay of 750ps ■ IEE min. of –25mA ■ Industry standard 100K ECL levels ■ Extended supply voltage option: VEE = –4.2V to –5.5V The SY100S301 is an ultra-fast triple 5-input OR/NOR

F100K

Abstract: SY100S336 SY100S336FC SY100S336JC SY100S336JCTR
Contextual Info: 4-STAGE COUNTER/ SHIFT REGISTER FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTION The SY100S336 functions either as a modulo-16 up/ down counter or as a 4-bit bidirectional shift register and is designed for use in high-performance ECL systems. Three

F100K

Abstract: SY100S321 SY100S321FC SY100S321JC SY100S321JCTR
Contextual Info: LOW-POWER 9-BIT INVERTER FEATURES SY100S321 DESCRIPTION • Max. propagation delay of 700ps ■ IEE min. of –55mA ■ Extended supply voltage option: VEE = –4.2V to –5.5V ■ Voltage and temperature compensation for improved noise immunity ■ 70% faster than Fairchild 300K at lower power

F100K

Abstract: SY100S302 SY100S302FC SY100S302JC SY100S302JCTR
Contextual Info: QUINT 2-INPUT OR/NOR GATE FEATURES The SY100S302 offers five 2-input OR/NOR gates designed for use in high-performance ECL systems. The five gates are controlled by a common Enable signal. All inputs have 75KΩ pull-down resistors and all outputs are buffered.

F100K

Abstract: SY100S350 SY100S350FC SY100S350FCTR SY100S350JC
Contextual Info: Micrel, Inc. SY100S350 FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ SY100S350 HEX D-LATCH DESCRIPTION The SY100S350 offers six high-speed D-Latches with both true and complement outputs, and is performance compatible for use with high-performance ECL systems.

Contextual Info: * TRIPLE 5-INPUT OR/NOR GATE SYNERGY SEMICONDUCTOR DESCRIPTION FEATURES Max. propagation delay of 750ps Iee SY100S301 min. o f-25 m A Industry standard 100K ECL levels T h e S Y 1 0 0 S 3 0 1 is an u ltra -fa s t triple 5 -in p u t O R /N O R g a te d e s ig n e d for use in h ig h -p e rfo rm a n c e E C L system s.

Contextual Info: * 16-INPUT MULTIPLEXER SYNERGY SY100S364 SEMICONDUCTOR FEATURES DESCRIPTION Max. propagation delay of 1300ps The SY100S364 is a 16-input m ultiplexer designed for use in high-perform ance ECL system s. The four Data Select inputs So, S i , S 2 , S 3 determ ine the bit from the 16

Contextual Info: TRIPLE 4-INPUT MULTIPLEXER WITH ENABLE SYNERG Y SY100S371 SEMICONDUCTOR DESCRIPTION FEATURES Max. propagation delay of 1000ps I e e min. of-68m A The SY100S371 is an ultra-fast triple 4-input multiplexer with true and complementary outputs designed for use in

Contextual Info: ENHANCED 4-STAGE COUNTER/SHIFT REGISTER SYNERG Y SY100S336A SEMICONDUCTOR FEATURES DESCRIPTION Max. shift frequency of 700MHz Clock to Q delay max. of 1100ps Sn to TC speed improved by 50% Sn set-up and hold time reduced by more than 50% Iee min. of -170m A

SY100S370

Abstract: transistor z2b Z4 13 F100K SY100S370FC SY100S370JC SY100S370JCTR Z745
Contextual Info: UNIVERSAL DEMULTIPLEXER/ DECODER FEATURES SY100S370 DESCRIPTION • Max. propagation delay of 1200ps ■ IEE min. of –92mA ■ Industry standard 100K ECL levels ■ Extended supply voltage option: VEE = –4.2V to –5.5V ■ Voltage and temperature compensation for improved

Contextual Info: * SYNERGY LOW-POWER HEX TTL-TO-PECL TRANSLATOR SY100S391 SEMICONDUCTOR DESCRIPTION FEATURES Operates from a single +5V supply Differential PECL outputs Companion chip to SY100S390 PECL-to-TTL translator Function and pinout compatible with National and Signetics F100K

MARKING d2b

Abstract: SY100S318FC SY100S318FCTR SY100S318JC SY100S318JCTR F100K SY100S318 D1C marking
Contextual Info: 5-WIDE 5, 4, 4, 4, 2 OA/OAI GATE Micrel, Inc. SY100S318 SY100S318 DESCRIPTION FEATURES • Max. propagation delay of 800ps ■ IEE min. of –55mA ■ Extended supply voltage option: VEE = –4.2V to –5.5V ■ Voltage and temperature compensation for improved noise immunity

Contextual Info: £* 4-STAGE COUNTER/ SHIFTREGISTER SYNERGY SEMICONDUCTOR SY100S336 SY101S336 PRELIMINARY DESCRIPTION FEATURES The SY100/101S336 functions either as a modulo-16 up/down counter or as 4-bit bidirectional shift register and is designed for use in high performance E C L systems. Three Select inputs Sn

Contextual Info: * 9-BIT BUFFER SYNERGY SY100S322 SEMICONDUCTOR DESCRIPTION FEATURES T h e S Y1O O S 322 is an u ltra -fa s t b u ffe r d e s ig n e d fo r u se in h ig h -p e rfo rm a n c e E C L s y s te m s . T h e d e v ic e p ro v id e s n in e n o n -in v e rtin g b u ffe rs w ith s in g le -e n d e d o u tp u ts . T h e

Contextual Info: LOW-POWER HEX TTL-TO-PECL TRANSLATOR SYNERGY SY100S391 SEMICONDUCTOR FEATURES DESCRIPTION • Operates from a single +5V supply The SY100S391 is a hex TTL-to-PECL translator for converting TTL logic levels to 100K logic levels. The unique feature of this translator is the ability to do this

Contextual Info: * QUINT DIFFERENTIAL LINE RECEIVER SYNERGY SY100S314 SEMICONDUCTOR DESCRIPTION FEATURES • Max. propagation delay of 900ps ■ Differential outputs ■ Ie e min. o f-60m A ■ ESD protection of 2000V ■ Extended supply voltage option: — VEE = -4.2V to -5.46V

Contextual Info: « LOW-POWER HEX PECL-TO-TTL TRANSLATOR SYNERGY SEMICONDUCTOR FE A T U R E S PRELIMINARY SY100S390 DESCRIPTION The SY100S390 is a hex PECL-to-TTL translator for converting 100K logic levels to TTL logic levels. Unlike other level translators, the SY100S390 operates using only one

Contextual Info: •C* QUINT 2-INPUT OR/NOR GATE SYNERGY SEMICONDUCTOR SY100S302 SY101S302 PRELIMINARY FEATURES • ■ ■ ■ ■ ■ ■ 700 ps max. Propagation Delay. Enable to Output max. of 900 ps. I ee mln. of -4 5 mA. ESD protection of 2000 V. Industry standard 100K ECL levels.

Contextual Info: TRIPLE 4-INPUT MULTIPLEXER WITH ENABLE SYNERGY SEMICONDUCTOR SY100S371 SY101S371 ADVANCE INFORMATION DESCRIPTION FEATURES The SY100/101S371 is an ultra-fast triple, 4-input multiplexer with true and complementary outputs, designed for use in high performance ECL systems. The multiplexers are controlled by

Contextual Info: * QUINT EXCLUSIVE OR/NOR GATE SYNERGY SY100S307 SEMICONDUCTOR FEATURES DESCRIPTION The SY100S307 is an ultra-fast quint exclusive-OR/ NOR gate designed for use in high-performance ECL systems. A function output that is the wire-OR result of the exclusive-OR outputs is also available. The inputs

Contextual Info: « LOW-P'OWERHEX TTL-TO-PECL TRANSLATOR SYNERGY PRELIMINARY SY100S391 SEMICONDUCTOR FEATURES DESCRIPTION The SY100S391 is a hex TTL-to-PECL translator for converting TTL logic levels to 100K logiclevels. Theunique feature of this translator is the ability to do this translation

Contextual Info: Q UINT EXCLUSIVE OR/NO R GATE SYNERGY SY100S307 SEMICONDUCTOR FEATURES DESCRIPTION • Max. propagation delay of 1000ps ■ I ee mln. of -58mA ■ ESD protection of 2000V ■ Extended supply voltage option: — VEE = -4.2V to 5.46V ■ Voltage and temperature compensation for