SUBLAYER Search Results

DP83223V

Abstract: t592 PE-68515L s558-5999-46 "network interface cards" "Fast Link Pulse"
Contextual Info: DP83846A DP83846A DsPHYTER - Single 10/100 Ethernet Transceiver Literature Number: SNLS063E DP83846A DsPHYTER — Single 10/100 Ethernet Transceiver General Description Features The DP83846A is a full feature single Physical Layer device with integrated PMD sublayers to support both

8B10B

Abstract: C035 CL45 P802 TLK3138
Contextual Info: TLK3138 www.ti.com SLLS762C – FEBRUARY 2007 – REVISED DECEMBER 2009 Dual XAUI Transceiver Check for Samples: TLK3138 • • • • • • • • 1 XGMII Extender Sublayer APPLICATIONS • 10 Gigabit Ethernet Servers and Routers TLK3138 TCLK(0) TD(31.0)

parallel to serial conversion

Abstract: diode 1432
Contextual Info: Temic COMLIB MATRA MHS ATM Physical Layer ASIC Macro Library for 1.432 Description The ASIC Macro Library is consisting of specific macros which are supporting the ATM 1.432 Physical M edium Sublayer up to 622 MBit/s serial communication. This macro family, which is targeted

Contextual Info: Advance Data Sheet August 1998 LU5M31 Gigabit Ethernet Media Access Controller MAC Overview The LU5M31 is a single-port 1 Gbit/s MAC that incorporates physical coding sublayer (PCS) functionality. The LU5M31 is intended to enhance 10/ 100 Mbits/s Ethernet frame switching, multiple port

st6116

Abstract: IC 7400 data sheet mh 7400 93C95A ATM25 TM25
Contextual Info: 93C95A ATM 25.6 MB Transceiver Technology, ,„ c o ,p o „ » d a n d D g ta R e C O V e ry lC April 8,1996 Features • Integrated A TM25 PMD Sublayer ■ Single Chip Interface Between TC Transmission

SES N 2402

Abstract: st6116 IC 7400 data sheet 93C95 93C95A ATM25 TM25 108404
Contextual Info: 93C95 ATM 25.6 MB Transceiver and Data Recovery 1C Technology, Incorporated PRELIMINARY Features • Integrated ATM 25 PMD Sublayer ■ Single Chip Interface Between TC Transmission Convergence A nd Twisted Pair Wire ■ ■ ■ ■ ■ ■ On Chip Transmit Wave Shaping A nd Filters

circuit diagram of PAM transmitter and receiver

Abstract: PAM-5 17-LEVEL 1000base high speed line driver GMII layout
Contextual Info: Preliminary - Content Subject to Change L80601 Ultra Low Power 10/100/1000 Mbits/s PHY Preliminary Datasheet The L80601 is a full-featured Physical Layer PHY transceiver with integrated Physical Media Dependent (PMD) sublayers to support 10BASE-T, 100BASE-TX, and 1000BASE-T Ethernet protocols.

Contextual Info: Â - ' PHY TC-PMD for 25.6 and 51.2 Mbps ATM Networks fffJSX Wdt) IDT77105 In teg rated D evice Technology, Inc. DESCRIPTION FEATURES • Performs the PHY-Transmission Convergence (TC) and Physical Media Dependent (PMD) Sublayer functions for 25.6 Mpbs and 51.2 Mbps ATM Networks

100BASE-FX

Abstract: DP83843 DP83843VJE t424
Contextual Info: July 1998 DP83843 PHYTER General Description Features The DP83843 is a full feature Physical Layer device with integrated PMD sublayers to support both 10BASE-T and 100BASE-X Ethernet protocols. • IEEE 802.3 ENDEC with AUI/10BASE-T transceivers and filters built-in

s40c

Abstract: CRC-32
Contextual Info: µ PD98409 ATM LIGHT SAR CONTROLLER NEASCOT-S40CTM Features • Conforms to the ATM-Forum recommendations • Implements PCI bus interface (5/3.3 V, 32-bit, 33 MHz): PCI Specification Revision 2.1 compliant • Implements AAL-5 SAR sublayer and ATM layer

x23 umi

Abstract: x22 umi fpga vhdl code for crc-32 umi x22 H440 CRC32 CRC-32 P802 k4107 0180C2000001
Contextual Info: ispLever CORE TM LatticeSCM Ethernet flexiMAC MACO Core User’s Guide September 2009 ipug48_01.8 LatticeSCM Ethernet flexiMAC MACO Core User’s Guide Lattice Semiconductor Introduction The LatticeSCM Ethernet flexiMAC™ MACO™ IP core assists the FPGA designer’s efforts by providing pretested, reusable functions that can be easily plugged in, freeing designers to focus on their unique system architecture. These blocks eliminate the need to “re-invent the wheel,” by providing either an industry-standard Layer 2 flexible packet framer and parser or a Layer 1 multi-protocol functionality of the Physical Coding Sublayer PCS

AF2.5 din 74

Contextual Info: TNETX4090 ThunderSWITCH II 9-PORT 100-/1OOO-MBIT/S ETHERNET™ SWITCH • Single-Chip 100-/1000-Mbit/s Device • • Integrated Physical Coding Sublayer PCS Logic Provides Direct Interface to Gigabit Transceivers Port Trunking/Load Sharing for High-Bandwidth Interswitch Links

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD98402A LOCAL ATM SONET FRAMER The µPD98402A is one of the ATM-LAN LSIs and incorporates the TC sublayer function in the SONET/SDHbased physical layer of the ATM protocol. The main functions of the µPD98402A include a transmit function for

Contextual Info: NWK935 100Base-TX Ethernet Physical Coding Sublayer DS4409 - 1.3 May 1996 The NWK935 is manufactured on Zarlink Semiconductors' 0.8µm CMOS process. The device will be available in a QFP package. GND2 17 NC 18 RDAT4 19 RDAT3 20 RDAT2 21 RDAT1 22 RDAT0 23 T25 24

prng

Abstract: 77V106 IDT77V106 IDT77V106L25 PE-67583 TLA-6M103
Contextual Info: IDT77V106L25 3.3V ATM PHY for 25.6 and 51.2 Mbps Features ! ! ! ! ! ! ! ! ! ! ! ! ! Description Performs the PHY-Transmission Convergence TC and Physical Media Dependent (PMD) Sublayer functions of the Physical Layer Compliant to ATM Forum (af-phy-040.000) and ITU-T I.432.5

XGXS

Abstract: 8B10B MHz 8B10B ORT82G5
Contextual Info: 10 Gigabit Ethernet XGXS Intellectual Property Core April 2003 Product Brief Overview The 10 Gigabit ethernet eXtender Sublayer XGXS Intellectual Property (IP) Core enables creation of system solutions for 10 Gigabit Ethernet applications as defined by IEEE 802.3ae. This IP Core targets the programmable

Contextual Info: DP83843 DP83843 PHYTER Literature Number: SNLS021A DP83843BVJE PHYTER General Description Features O bs ol et e The DP83843BVJE is a full feature Physical Layer device — IEEE 802.3 ENDEC with AUI/10BASE-T transceivers with integrated PMD sublayers to support both 10BASE-T

IDT77V1264L200

Contextual Info: IDT77V1264L200 Quad Port PHY Physical Layer for 25.6, 51.2, and 204.8 Mbps ATM Networks and Backplane Applications Description Features List ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ ‹ Performs the PHY-Transmission Convergence (TC) and Physical Media Dependent (PMD) Sublayer functions for

"network interface cards"

Contextual Info: DP83846A DsPHYTER — Single 10/100 Ethernet Transceiver General Description Features The DP83846A is a full feature single Physical Layer device with integrated PMD sublayers to support both 10BASE-T and 100BASE-TX Ethernet protocols over Category 3 10 Mb/s or Category 5 Unsheilded twisted pair

1000BASE-X

Abstract: vhdl code for defer block coding in mac transmitter verilog code for mdio protocol verilog code for MII phy interface DS200 xip2150 xilinx tcp vhdl
Contextual Info: zozo 1-Gigabit Ethernet MAC Core with PCS/PMA Sublayers 1000BASE-X or GMII v3.0 R DS200 (v1.1) April 30, 2003 Product Specification Features • LogiCORE Facts Single-speed 1-gigabit-per-second Ethernet Media Access Controller (MAC) Core Specifics •

loopback

Abstract: pcie loop back PCIe 8B10B
Contextual Info: 6. Loopback in Stratix V Devices SV52007-1.0 This chapter describes the two loopback options used on Stratix V GX and GS devices, which allow you to verify how different functional blocks work in the transceiver standard physical coding sublayer PCS . Standard PCS Loopback Configurations

XAPP759

Abstract: verilog code for fibre channel 1000BASE-X PPC405 Virtex-II Pro and Virtex-II Pro X Platform FPGAs Xuint32 CPCS BOARD POWER SUPPLY ML323 1000base-x xilinx DS264
Contextual Info: Application Note: Virtex-II Pro Family R Configurable Physical Coding Sublayer Author: Dai Huang, Jack Lo, and Shalin Sheth XAPP759 v1.1 March 4, 2005 Summary This application note describes a Configurable Physical Coding Sublayer (CPCS) reference design that extends the functionality of the Xilinx RocketIO multi-gigabit transceiver (MGT)

10Gbase-kr backplane connector

Abstract: Virtex-7 serdes virtex-7 Auto-Negotiation 10Gbase kr
Contextual Info: LogiCORE IP 10-Gigabit Ethernet PCS/PMA v2.3 DS739 April 24, 2012 Product Specification Introduction The LogiCORE IP 10-Gigabit Ethernet Physical Coding Sublayer/Physical Medium Attachment PCS/PMA core forms a seamless interface between the Xilinx 10-Gigabit Ethernet Media Access

TSC 232 CPE

Abstract: RS -12V SDS RELAY RS -24V SDS RELAY RSL -12V SDS RELAY univac DS1 frame synchronization CMI 1990 MS NAS DC standards parts cross reference coded mark inversion 1990 mtbf slc TCP 8026
Contextual Info: Philips Semiconductors Acronyms Networking acronyms A B ATM Adaptation Layer, two sublayers concerned with segmenting large PDUs into ATM cells; type 1 = CBR, 2 = VBR. See also SAR. B Bearer channel, a DS–0 for user trafrlc. BCC Block Check Code, a CRC or similarly calculated number