STM SUFFIX Search Results

TXC-07905

Abstract: AU-AIS MSP SNCP BP-51H TXC-07905BRBG 421L BY274
Contextual Info: OED622 Device Dual STM-4/STM-1 Overhead Terminator, Tributary Processor and Cross-Connect with Integrated E1 Mapper TXC-07905 DATA SHEET DESCRIPTION: ™ The Optimized Edge Device, OED622, is a dual STM-4/STM-1 SDH framer and overhead terminator, virtual

prbs parity checker and generator

Abstract: RGPI5 4-bit even parity checker circuit diagram BY339 relay cross reference AC03 nec SDH 209 XRT95L34 XRT95L34IV b20 p03
Contextual Info: áç PRELIMINARY XRT95L34 OC-12/STM-4, QUAD OC-3/STM-1 POS/ATM FRAMER WITH INTEGRATED CDR’S APRIL 2002 GENERAL DESCRIPTION The XRT95L34 is an OC-12/STM-4, Quad OC-3/ STM-1 POS/ATM Framer with integrated CDR’s. ATM direct mapping and cell delineation are supported, so

GG1Q

Contextual Info: DATASHEET PM PMC-970133 ISSUE2 PRELIMINARY 1 PMC-Sierra, Inc. PMS342 spbctra -155 SONET/SDH PA YLOAD EXTRACTOR/ALIGNER FEATURES • Monolithic SONET/SDH PAYLOAD EXTRACTOR/ALIGNER for use in STS-1 STM-0/AU3 , STS-3 (STM-1/AU3) or STS-3c (STM-1 /AU4) interface

Contextual Info: EtherPHAST -48 Plus Device OC-48/STM-16 SONET/SDH Ethernet Mapper TXC-06742 DATA SHEET PRODUCT PREVIEW TXC-06742-MB, Ed. 4 December 2005 FEATURES APPLICATIONS • 1x STS-48/STM-16 or 4x STS-12/STM-4 framer with TOH processing, 4x 622 LVDS line side interface

ICS894D115I-04

Abstract: led clock circuit diagram ICS894D115I-01 ICS894D115AGI-04 ICS894D115I
Contextual Info: ICS894D115I-04 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE General Description Features The ICS894D115I-04 is a clock and data recovery circuit. The device is designed to extract the clock HiPerClockS signal from a NRZ-coded STM-4 OC-12/STS-12 or

Contextual Info: ICS894D115I-04 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE General Description Features The ICS894D115I-04 is a clock and data recovery circuit. The device is designed to extract the clock HiPerClockS signal from a NRZ-coded STM-4 OC-12/STS-12 or

ICS894D115I-01

Abstract: tube OC3 ICS894D115BGI-01 ICS894D115I-04 ICS894D115I vsc8115 OC3 Tube
Contextual Info: ICS894D115I-01 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE General Description Features The ICS894D115I-01 is a clock and data recovery circuit. The device is designed to extract the clock HiPerClockS signal from a NRZ-coded STM-4 OC-12/STS-12 or

OC3 Tube

Abstract: C813C Nippon capacitors
Contextual Info: PRELIMINARY ICS894D115I-01 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE General Description Features The ICS894D115I-01 is a clock and data recovery circuit. The device is designed to extract the clock HiPerClockS signal from a NRZ-coded STM-4 OC-12/STS-12 or

Contextual Info: ICS894D115I-01 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE General Description Features The ICS894D115I-01 is a clock and data recovery circuit. The device is designed to extract the clock HiPerClockS signal from a NRZ-coded STM-4 OC-12/STS-12 or

E4 smd

Abstract: Diodes smd e4 TG04-TDK2NS TG04-TDK1N1 78P2253 STM-1
Contextual Info: SMD E4/STM-1/STS-3/OC-3 Modules SMD E4/STM-1/STS-3/OC-3 Modules HALO Electronics has developed this standard series of single and dual core devices to meet the requirements for E4, STM-1, STS-3 and OC-3 applications. Designed specifically to interface with the TDK 78P2253 transceiver. UL1950, IEC950 and EN60950

Contextual Info: DATA SHEET PM PMC-970133 ISSUE 4 1 PMC-Sierra, Inc. PM5342 s p e c t r a -155 SONET/SDH PA YLOAD EXTRACTOR/ALIGNER FEATURES • Monolithic SONET/SDH PAYLOAD EXTRACTOR/ALIGNER for use in STS-1 STM-0/AU3 , STS-3 (STM-1/AU3) or STS-3c (STM-1/AU4) interface applications, operating at serial interface speeds of up to 155.52 Mbit/s.

LXT6155

Abstract: smd 6287 SMD e4 w Diodes smd e4 E4 SMD TX3044 TX3044T T1162
Contextual Info: SONET/SDH Dual Line Interface Transformer for E4/STM-1 Applications Supports 139.264 E4 and 155.52 (STM-1) Mbps for Coded Mark Inversion (CMI) interfaces Designated to interface with Intel’s LXT6155 for use with 75Ω coaxial cable Excellent Return Loss performance

diode GFP AA

Abstract: KT 208 sierra The SDH interface in AXE MQE vco ss19 810 DD107* CONVERTER WD 969 TAA 611 T12 ic tb 810 datasheet hp 9720
Contextual Info: D A TA S H E E T PM PM C -970133 IS S U E 2 n /K PR ELIM INA R Y 1 PMC-Sierra, Inc. PM5342 s p e c tra -155 SO N ET/SDH PA YLO AD EXTRACTO R/ALIG NER FEATURES • Monolithic SONET/SDH PAYLOAD EXTRACTOR/ALIGNER for use in STS-1 STM-0/AU3 , STS-3 (STM-1/AU3) or STS-3c (STM-1/AU4) interface

16 byte register VERILOG

Abstract: verilog code BIP-8 GR-253 GR-253-CORE STS12CFRM digital alarm clock vhdl code in modelsim alarm clock design of digital VHDL
Contextual Info: SONET/SDH STS-12c/STM-4 Framer MegaCore Function STS12CFRM July 2001 User Guide Version 1.01 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com A-UG-IPSTS12CFRM-1.01 SONET/SDH STS-12c/STM-4 Framer MegaCore Function (STS12CFRM) User Guide

smd 6287

Abstract: LXT6155 Diodes smd e4 E4 SMD TX3044 TX3044T R675
Contextual Info: SONET/SDH Dual Line Interface Transformer for E4/STM-1 Applications Supports 139.264 E4 and 155.52 (STM-1) Mbps for Coded Mark Inversion (CMI) interfaces Designed to interface with Intel’s LXT6155 for use with 75 Ω coaxial cable Excellent Return Loss performance

Contextual Info: SONET/SDH Dual Line Interface Transformer for E4/STM-1 Applications Supports 139.264 E4 and 155.52 (STM-1) Mbps for Coded Mark Inversion (CMI) interfaces Designated to interface with Intel’s LXT6155 for use with 75Ω coaxial cable Return Loss meets G.703 requirements

CX950

Abstract: 0X351
Contextual Info: CX29610 OptiPHYTM - M622 STS-12/4x STS-3 SONET/SDH Multiplexer Distinguishing Features • • • • • Processes combinations of STS-12, STS-3 payload framing/multiplexing for: – 1x STS-12/STM-4 – 4x STS-3/STM-1 Glueless connectivity to the CX29503/CX29513 and

LXT6155

Abstract: ST6200QNL mark code e4 diode
Contextual Info: SONET/SDH Dual Line Interface Transformer for E4/STM-1 Applications Supports 139.264 E4 and 155.52 (STM-1) Mbps for Coded Mark Inversion (CMI) interfaces Designed to interface with Intel’s LXT6155 for use with 75Ω coaxial cable Dual design supports transmit and receive circuitry

234h

Abstract: GR-253 TRCV012G5 TRCV012G7 TTRN012G5 TTRN012G7
Contextual Info: Preliminary Data Sheet August 2000 TRCV012G5 2.5 Gbits/s and TRCV012G7 (2.5 Gbits/s and 2.7 Gbits/s) Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer Features • TRCV012G5 supports OC-48/STM-16 data rate ■ TRCV012G7 supports: — OC-48/STM-16 data rate

Contextual Info: DATA SHEET p iv PMC-930829 ISSUE 5 1 r PMC-Sierra, Inc. PM5312 sttx SONET/SDH TRANSPORT TERMINA TING TRANSCEIVER FEATURES • Monolithic SONET/SDH Transport Overhead Terminating Transceiver for use in STS-1, STS-3 STM-1 , or STS-12 (STM-4) line interface applications.

Contextual Info: Product Specification Single Mode 622 Mbit/s ATM/SDH/SONET 1x9 Transceiver Extended Temperature Range –40°C to 85°C V23826-H18-C366 PRODUCT FEATURES • Compliant with ATM, SONET OC-3, SDH STM-1 and SONET OC-12, SDH STM-4 • Meets mezzanine standard height of

a105 transistor

Abstract: ST6200T transistor a105 mark code e4 diode LXT6155 smd PULSE TRANSFORMER SMD 5 PIN CODE E4 a105 A105 Board a105 SMD transistor
Contextual Info: SONET/SDH Dual Line Interface Transformer for E4/STM-1 Applications Compliant with ITU-T/G.703 Supports 139.264 E4 and 155.52 (STM-1) Mbps for Coded Mark Inversion (CMI) interfaces Designed to interface with Level One’s LXT6155 for use with 75 W coaxial cable

c366

Abstract: V23826-H18-C366 stm4 infineon
Contextual Info: Fiber Optics DC/DC 3.3V Single Mode 622 MBd ATM/SDH/SONET 1x9 Transceiver Extended Temperature Range (–40°C to 85°C) V23826-H18-C366 Features • Compliant with ATM, SONET OC-3, SDH STM-1 and SONET OC-12, SDH STM-4 • Meets mezzanine standard height of 9.8 mm

Contextual Info: Fiber Optics V23826-H18-C366 Single Mode 622 Mbit/s ATM/SDH/SONET 1x9 Transceiver Extended Temperature Range –40°C to 85°C Features • Compliant with ATM, SONET OC-3, SDH STM-1 and SONET OC-12, SDH STM-4 • Meets mezzanine standard height of 9.8 mm