ST ZD 125 Search Results
ST ZD 125 Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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IHA910
Abstract: octal optocoupler ZD 260
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8S9000 BS9Q00 BS5750/IS09000/EN29000 IHA910 octal optocoupler ZD 260 | |
Contextual Info: IS42G32256_ 256K x 32 x 2 16-Mbit SYNCHRONOUS GRAPHICS RAM ADVANCE INFORMATION APRIL 1998 FEATURES • Operating frequency: 125 MHz • 256,144 words x 32 bits x 2-bank organization • Programmable special register - Graphic cycles • Dual internal bank control |
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IS42G32256_ 16-Mbit) SR037-0B IS42G32256 IS42G32256-8TQ IS42G32256-1OTQ | |
Contextual Info: Z9104 Variable Delay Motherboard Clock Buffer Preliminary PRODUCT FEA TURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ Output phase relationship is precisely controllable with respect to input clock via a dedicated external feedback path. 6 Low Skew Clocks Generated |
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Z9104 32-Lead Z9104CAB Z9104CAB, | |
Contextual Info: f i l i Z9104 IH rJli v H I H « • '* i i s f isa W Variable Delay Motherboard Clock Buffer Preliminary PRODUCT FEA TURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ Output phase relationship is precisely controllable with respect to input clock via a dedicated external feedback path. |
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Z9104 32-Lead Z9104AAB Z9104AAB, | |
Contextual Info: Z9102 Variable Delay Motherboard Clock Buffer Approved Product PRODUCT FEA TURES • ■ ■ ■ ■ ■ ■ ■ ■ Output phase relationship is precisely controllable with respect to input clock via a dedicated external feedback path. 6 Low Skew Clocks Generated |
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Z9102 32-Lead Z9102BAB Z9102BAB, | |
Contextual Info: MM! Z9102 mñMi Variable Delay Motherboard Clock Buffer Approved Product PRODUCT FEA TURES • ■ ■ ■ ■ ■ ■ ■ ■ Output phase relationship is precisely controllable with respect to input clock via a dedicated external feedback path. 6 Low Skew Clocks Generated |
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Z9102 32-Lead Z9102AAB Z9102AAB, | |
Contextual Info: Vpp¤4^ phz¤F p=Fd¬s¬:¬T¬§a^^F F" aFd= h"VamVp¤4^4FFm FFOFFm4F pz aV^ ^ah"m¤"da;snn ©m"zpF4^mpdpVaF m4 ddaV^FF¦F= |
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Contextual Info: Z9102 Fï Variable Delay Motherboard Clock Buffer Approved Product PRODUCT FEA TURES • ■ ■ ■ ■ ■ ■ ■ ■ Output phase relationship is precisely controllable with respect to input clock via a dedicated external feedback path. 6 Low Skew Clocks Generated |
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32-Lead Z9102 Z9102AAB Z9102AAB, | |
Contextual Info: L7C162 16K x 4 Static R A M FEATURES □ 16K x 4 Static RAM with Separate I/O and High Impedance Write □ Auto-Powerdown Design □ Advanced CMOS Technology □ High Speed — to 12 ns maximum □ Low Power Operation Active: 325 mW typical at 25 ns Standby: 400 [iW typical |
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L7C162 MIL-STD-883, CY7C162 28-pin L7C162 L7C162CM25 L7C162CM20 | |
Contextual Info: s p p p :•u e GOOGrT'cn FILM TRIM P LA S TIC D IELEC TR IC C APACITORS S G -402G 10 m m TOP & BO TTO M / S ID E A D JU ST Voltage Rating: High Temperature PTFE — 200 WVDC, all others — 100 W VDC Dielectric Withstanding Voltage: High Temperature PTFE — |
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-402G | |
Contextual Info: HN58V65A Series HN58V66A Series 8192-word x 8-bit Electrically Erasable and Programmable CMOS ROM HITACHI ADE-203-539A Z Rev. 1.0 Aug. 28, 1997 Description The Hitachi HN58V65A series and HN58V66A series are a electrically erasable and programmable EEPROM’s organized as 8192-word x 8-bit. They have realized high speed, low power consumption and |
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HN58V65A HN58V66A 8192-word ADE-203-539A 64-byte | |
Contextual Info: KM48V512B/BL/BLL CMOS DRAM 512K x 8 Bit CMOS Dynamic RAM with Fast Page Mode FEATURES GENERAL DESCRIPTION The S a m sun g K M 4 8V 51 2 B /B L V B L L is a C M O S high s p e e d 5 2 4 ,2 8 8 b i t x 8 D y n a m ic R a n d o m A c c e s s • Performance range: |
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KM48V512B/BL/BLL 110ns 130ns 150ns 28-LEAD | |
mb88625b
Abstract: MB88625B-PF MBM27C256A-25CZ D64001S-3C P Channel Equivalent to buz 350 MBM27C256A-25CV MB88625B-PSH pa2al MB886 GD03
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GD03131 MB88620B Vco-40V 12K/16K MQP-64C-P01) 4g-T9-44 M64004S-1C mb88625b MB88625B-PF MBM27C256A-25CZ D64001S-3C P Channel Equivalent to buz 350 MBM27C256A-25CV MB88625B-PSH pa2al MB886 GD03 | |
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA 16K x 16 Bit Cache Tag RAM for PowerPC Processors The MPC27T416 is a 262,144 bit cache-tag static RAM designed to support PowerPC microprocessors at bus speeds up to 66 MHz. It is organized as 16K words of 16 bits each. There are 14 common I/O tag bits and 2 separate I/O |
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MPC27T416 14-bit MPCZ7T416 27T416 MPC27T416TQ9 MPC27T416TQ9R MPC27T416TQ10 MPC27T416TQ10R MPC27T416TQ12 | |
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Contextual Info: L7C164/166 16K x 4 Static R A M FEATURES DESCRIPTION □ 16K x 4 Static RAM with Common I/O □ Auto-Powerdown Design □ Advanced CMOS Technology □ High Speed — to 12 ns maximum □ Low Power Operation Active: 325 mW typical at 25 ns Standby: 400 iW typical |
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L7C164/166 L7C164 L7C166 MIL-STD-883, CY7C164/166 24-pin 22/24-pin 22/28-pin | |
Contextual Info: L 7 C 1 9 4 /1 9 5 64K x 4 Static RAM D E V IC E S IN C O R P O R A T E D DESCRIPTION FEATURES □ 64K x 4 Static RAM with Common I/O □ Auto-Powerdown Design □ Advanced CMOS Technology □ High Speed — to 15 ns maximum □ Low Power Operation Active: 210 mW typical at 35 ns |
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L7C194 MIL-STD-883, CY7C194/195 24/28-pin 28-pin L7C194 L7C195 00Q22b2 | |
Contextual Info: L7C164/166 \}\v s DESCRIPTION FEATURES □ 16K x 4 Static RAM with Common I/O □ Auto-Powerdown Design □ Advanced CMOS Technology □ High Speed — to 12 ns maximum □ Low Power Operation Active: 325 mW typical at 25 ns Standby: 400 |iW typical □ Data Retention at 2 V for Battery |
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L7C164/166 L7C164 L7C166 MIL-STD-883 L7C166CMB25 L7C166CMB20 L7C166CMB15 | |
Contextual Info: MX23C1 611 16M-BIT MASK ROM 8/16 BIT OUTPUT FEATURES ORDER INFORMATION • Bit organization - 2M x 8 (byte mode) - 1M x 16 (word mode) • Fast access time - Random access: 100ns (max.) - Page access: 50ns (max.) • Page Size - 8 double words per page • Current |
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MX23C1 16M-BIT 100ns 100uA 500mil) 600mm) MX23C1611MC-10 MX23C1611MC-12 MX23C1611PC-10 MX23C1611PC-12 | |
Contextual Info: L7C108/109 128K x 8 Static RAM Low Power ;• v .• s [. : j ;i’[ : <a DESCRIPTION FEATURES □ 128K x 8 Static RAM with Chip Select Powerdown, Output Enable □ Auto-Powerdown Design □ Advanced CMOS Technology □ High Speed — to 15 ns maximum |
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L7C108/109 L7C108 L7C109 L7C109KC25* L7C109KC20* L7C109KC17* | |
Contextual Info: 8 Megabit CMOS SRAM M I C R O S Y S T E MS DPS1MS8MP DESCRIPTION: The D PS1M S8M P is a 1Meg x 6 high-density, low-power static RAM module comprised of two 512K x 8 monolithic SRAM's, an advanced high-speed CMOS decoder and decoupling capacitors surface mounted on |
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600-mil-wide, 32-pin 30A143-00 | |
ES981
Abstract: WAVETABLE
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ES690 16-bit ES981 SAM0Q13 WAVETABLE | |
DP-64S
Abstract: FP-80B HD81901 HD81901CPS2 HD81901FS2 HD81901PS2 V27bis D2738 d2144
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HD81901 27ter/bis 26/bis 26/bis DP-64S FP-80B HD81901CPS2 HD81901FS2 HD81901PS2 V27bis D2738 d2144 | |
B047
Abstract: L162 V7-1A27D8-207
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V7-1A27D8-207 CW-B0470 5M-1982 FORCE---86 1/10HP B047 L162 V7-1A27D8-207 | |
hitachi h1
Abstract: 66204TFL HD66204TF
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HD66204 HD66204F/HD66204FL/HD66204TF/HD 66204TFL, HD66204 HD66204F, HD66204FL, HD66204TF HD66204TFL, hitachi h1 66204TFL |