SSOP PACK D12 Search Results

transistor SR 13001

Abstract: RCA SK CROSS-REFERENCE PCD8572I ATmel 730 24c04 SR 13001 transistor atmel 716 24c04 UNITRODE applications handbook uc3842 -96 all 89c51 microcontroller references book QFP44 footprint HI5618
Contextual Info: INTEGRATED CIRCUITS DATA SHEET PCF5001 POCSAG Paging Decoder Product specification Supersedes data of 1995 Apr 27 File under Integrated Circuits, IC17 1997 Mar 04 Philips Semiconductors Product specification POCSAG Paging Decoder PCF5001 CONTENTS BLOCK DIAGRAMS

SN74ACT7814-20DLR

Abstract: 1M7814-40DLG4 SN74ACT7804 SN74ACT7806 SN74ACT7814 SN74ACT7814-20DL
Contextual Info: SN74ACT7814 64 x 18 STROBED FIRST-IN, FIRST-OUT MEMORY SCAS209C – APRIL 1992 – REVISED APRIL 1998 D D D D D D D D D D D Member of the Texas Instruments Widebus Family Load Clock and Unload Clock Can Be Asynchronous or Coincident 64 Words by 18 Bits

Contextual Info: PLL1700 PLL 170 49% FPO SBOS096A – JANUARY 1998 – REVISED MAY 2007 MULTI-CLOCK GENERATOR FEATURES DESCRIPTION ● 27MHz MASTER CLOCK INPUT The PLL1700 is a low cost, multi-clock generator Phase Lock Loop PLL . ● GENERATED AUDIO SYSTEM CLOCK: SCKO1: 33.8688MHz (Fixed)

vco 27MHz

Abstract: 74HC04 PCM1716 PLL1700 PLL1700E QUARTZ OSCILLATOR 27MHZ
Contextual Info: PLL1700 PLL 170 49% FPO SBOS096A – JANUARY 1998 – REVISED MAY 2007 MULTI-CLOCK GENERATOR FEATURES DESCRIPTION ● 27MHz MASTER CLOCK INPUT The PLL1700 is a low cost, multi-clock generator Phase Lock Loop PLL . ● GENERATED AUDIO SYSTEM CLOCK: SCKO1: 33.8688MHz (Fixed)

Contextual Info: PLL1700 PLL 170 49% FPO SBOS096A – JANUARY 1998 – REVISED MAY 2007 MULTI-CLOCK GENERATOR FEATURES DESCRIPTION ● 27MHz MASTER CLOCK INPUT The PLL1700 is a low cost, multi-clock generator Phase Lock Loop PLL . ● GENERATED AUDIO SYSTEM CLOCK: SCKO1: 33.8688MHz (Fixed)

Contextual Info: 19-1319; Rev 2; 6/07 KIT ATION EVALU E L B A AVAIL 2x4-Channel, Simultaneous-Sampling 14-Bit DAS Features The MAX125/MAX126 are high-speed, multichannel, 14-bit data-acquisition systems DAS with simultaneous track/holds (T/Hs). These devices contain a 14-bit, 3µs,

Contextual Info: Temic Semiconductors 16K X 16 Very Low Power SRAM TSM65686 Introduction The TSM65686 is a very low power CMOS static RAM organized as 16384x8x2 bits. It is manufactured using a high performance CMOS technology. With this process, TEMIC is the first to bring solutions for

Contextual Info: PLL1700 PLL 170 49% FPO SBOS096A – JANUARY 1998 – REVISED MAY 2007 MULTI-CLOCK GENERATOR FEATURES DESCRIPTION ● 27MHz MASTER CLOCK INPUT The PLL1700 is a low cost, multi-clock generator Phase Lock Loop PLL . ● GENERATED AUDIO SYSTEM CLOCK: SCKO1: 33.8688MHz (Fixed)

1M7813-25DLRG4

Abstract: SN74ACT7803 SN74ACT7805 SN74ACT7813 SN74ACT7813-15DL
Contextual Info: SN74ACT7813 64 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS199B – JANUARY 1991 – REVISED APRIL 1998 D D D D D D D D D D D D D Member of the Texas Instruments Widebus Family Free-Running Read and Write Clocks Can Be Asynchronous or Coincident Read and Write Operations Synchronized

SN74ACT7804

Abstract: SN74ACT7806 SN74ACT7814 W256
Contextual Info: SN74ACT7804 512 x 18 STROBED FIRST-IN, FIRST-OUT MEMORY SCAS204C – APRIL 1992 – REVISED APRIL 1998 D D D D D D D D D D D Member of the Texas Instruments Widebus Family Load Clock and Unload Clock Can Be Asynchronous or Coincident 512 Words by 18 Bits

Contextual Info: SN74ACT7813 64 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS199B – JANUARY 1991 – REVISED APRIL 1998 D D D D D D D D D D D D D Member of the Texas Instruments Widebus Family Free-Running Read and Write Clocks Can Be Asynchronous or Coincident Read and Write Operations Synchronized

Contextual Info: SN74ACT7803 512 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS191C – MARCH 1991 – REVISED APRIL 1998 D D D D D D D D D D D D D Member of the Texas Instruments Widebus Family Free-Running Read and Write Clocks Can Be Asynchronous or Coincident Read and Write Operations Synchronized

Contextual Info: PLL1705 PLL1706 SLES046A − AUGUST 2002 − REVISED SEPTEMBER 2002 3.3ĆV DUAL PLL MULTICLOCK GENERATOR FEATURES D 27-MHz Master Clock Input D Generated Audio System Clock: − SCKO0: 768 fS fS = 44.1 kHz − SCKO1: 384 fS, 768 fS (fS = 44.1 kHz) − SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2,

arduino nano

Abstract: mouser ATMEGA168 arduino ATMEGA168-20AU MBR0520LT1G SMD LD3 YC164-JR T491A475K010AT YC164-JR-07
Contextual Info: Arduino Nano V2.3 User Manual Released under the Creative Commons Attribution Share-Alike 2.5 License http://creativecommons.org/licenses/by-sa/2.5/ More information: www.arduino.cc Rev. 2.3 Arduino Nano Pin Layout ! D1/TX (1) D0/RX (2) RESET (3) GND (4)

Contextual Info: SN74ACT7814 64 x 18 STROBED FIRST-IN, FIRST-OUT MEMORY SCAS209C – APRIL 1992 – REVISED APRIL 1998 D D D D D D D D D D D Member of the Texas Instruments Widebus Family Load Clock and Unload Clock Can Be Asynchronous or Coincident 64 Words by 18 Bits

Contextual Info: PLL1705 PLL1706 SLES046A − AUGUST 2002 − REVISED SEPTEMBER 2002 3.3ĆV DUAL PLL MULTICLOCK GENERATOR FEATURES D 27-MHz Master Clock Input D Generated Audio System Clock: − SCKO0: 768 fS fS = 44.1 kHz − SCKO1: 384 fS, 768 fS (fS = 44.1 kHz) − SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2,

Contextual Info: SN74ACT7814 64 x 18 STROBED FIRST-IN, FIRST-OUT MEMORY SCAS209C – APRIL 1992 – REVISED APRIL 1998 D D D D D D D D D D D Member of the Texas Instruments Widebus Family Load Clock and Unload Clock Can Be Asynchronous or Coincident 64 Words by 18 Bits

PLL1705

Abstract: PLL1705DBQ PLL1705DBQR PLL1706 PLL1706DBQ PLL1706DBQR 4-pin 27mhz crystal ML marking
Contextual Info: PLL1705 PLL1706 SLES046A − AUGUST 2002 − REVISED SEPTEMBER 2002 3.3ĆV DUAL PLL MULTICLOCK GENERATOR FEATURES D 27-MHz Master Clock Input D Generated Audio System Clock: − SCKO0: 768 fS fS = 44.1 kHz − SCKO1: 384 fS, 768 fS (fS = 44.1 kHz) − SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2,

4-pin 27mhz crystal

Abstract: QUARTZ OSCILLATOR 27MHZ PLL1705 PLL1705DBQ PLL1705DBQR PLL1706 PLL1706DBQ PLL1706DBQR
Contextual Info: PLL1705 PLL1706 SLES046A − AUGUST 2002 − REVISED SEPTEMBER 2002 3.3ĆV DUAL PLL MULTICLOCK GENERATOR FEATURES D 27-MHz Master Clock Input D Generated Audio System Clock: − SCKO0: 768 fS fS = 44.1 kHz − SCKO1: 384 fS, 768 fS (fS = 44.1 kHz) − SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2,

Contextual Info: SN74ACT7814 64 x 18 STROBED FIRST-IN, FIRST-OUT MEMORY SCAS209C – APRIL 1992 – REVISED APRIL 1998 D D D D D D D D D D D Member of the Texas Instruments Widebus Family Load Clock and Unload Clock Can Be Asynchronous or Coincident 64 Words by 18 Bits

PLL1707-Q1

Contextual Info: PLL1707 PLL1708 SLES065 – DECEMBER 2002 3.3ĆV DUAL PLL MULTICLOCK GENERATOR FEATURES D 27-MHz Master Clock Input D Generated Audio System Clock PLL1707 : D D D D D D D D – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 768 fS, 512 fS (fS = 48 kHz) – SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2,

Contextual Info: PLL1707 PLL1708 SLES065 – DECEMBER 2002 3.3ĆV DUAL PLL MULTICLOCK GENERATOR FEATURES D 27-MHz Master Clock Input D Generated Audio System Clock PLL1707 : D D D D D D D D – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 768 fS, 512 fS (fS = 48 kHz) – SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2,

Block Diagram of dvd player

Abstract: block diagram of DVD PLL1708DBQR PLL1705 PLL1706 PLL1707 PLL1707DBQ PLL1707DBQR PLL1708 PLL1708DBQ
Contextual Info: PLL1707 PLL1708 SLES065 – DECEMBER 2002 3.3ĆV DUAL PLL MULTICLOCK GENERATOR FEATURES D 27-MHz Master Clock Input D Generated Audio System Clock PLL1707 : D D D D D D D D – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 768 fS, 512 fS (fS = 48 kHz) – SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2,

27MHz vco

Abstract: vco 27MHz 74HC04 PCM1716 PLL1700 PLL1700E PLL1700EG QUARTZ OSCILLATOR 27MHZ
Contextual Info: PLL1700 PLL 170 49% FPO SBOS096A – JANUARY 1998 – REVISED MAY 2007 MULTI-CLOCK GENERATOR FEATURES DESCRIPTION ● 27MHz MASTER CLOCK INPUT The PLL1700 is a low cost, multi-clock generator Phase Lock Loop PLL . ● GENERATED AUDIO SYSTEM CLOCK: SCKO1: 33.8688MHz (Fixed)