SRAM WITH ADDRESS COUNTER Search Results

M48T559Y

Abstract: M48T59 M4T28-BR12SH SOH28
Contextual Info: M48T559Y 5.0V, 64 Kbit 8 Kbit x 8 TIMEKEEPER SRAM WITH ADDRESS/ADDRESS/DATA MULTIPLEXED FEATURES SUMMARY • SOFTWARE and HARDWARE RESET FOR WATCHDOG TIMER ■ REGISTER COMPATIBLE WITH M48T59 TIMEKEEPER SRAM ■ ADDRESS/ADDRESS/DATA MULTIPLEXED ■ I/O PINS

Contextual Info: KM732V596A/L 32Kx32 Synchronous SRAM 32Kx32-Bit Synchronous Pipelined Burst SRAM FEATURES GENERAL DESCRIPTION Synchronous Operation. 2 Stage Pipelined operation with 4 Burst. On-Chip Address Counter. W rite Self-Timed Cycle. On-Chip Address and Control Registers.

KM732V588-15

Abstract: KM732V588-13
Contextual Info: KM732V588 32Kx32 Synchronous SRAM 32K X 32-Bit Synchronous Pipelined Burst SRAM FEATURES GENERAL DESCRIPTION • Synchronous Operation. • 2 Stage Pipelined operation with 4 Burst • On-Chip Address Counter. • Self-Timed Write Cycle. • On- Chip Address and Control Registers.

U111B

Abstract: KM732V588 KM732V588-13 KM732V588-15 KM732V588-17
Contextual Info: KM732V588 32Kx32 Synchronous SRAM 32K X 32-Bit Synchronous Pipelined Burst SRAM FEATURES GENERAL DESCRIPTION • Synchronous Operation. • 2 Stage Pipelined operation with 4 Burst • On-Chip Address Counter. • Self-Timed Write Cycle. • On- Chip Address and Control Registers.

Contextual Info: KM732V596A/L 32Kx32 Synchronous SRAM 32Kx32-Bit Synchronous Pipelined Burst SRAM FEATURES GENERAL DESCRIPTION •• Synchronous Operation. •• 2 Stage Pipelined operation with 4 Burst. •• On-Chip Address Counter. - Write Self-Timed Cycle. - On-Chip Address and Control Registers.

Contextual Info: Advance KM736V695/L 64Kx36 Synchronous SRAM 64K x 36-Bit Synchronous Pipelined Burst SRAM GENERAL DESCRIPTION FEATURES • Synchronous Operation. • 2 Stage Pipelined operation with 4 Burst • On-Chip Address Counter. • Self-Timed Write Cycle. • On- Chip Address and Control Registers.

7411 truth table

Contextual Info: Preliminary KM736V599A/L 32Kx36 Synchronous SRAM 32K x 36 - Bit Synchronous Pipelined Burst SRAM FEATURES GENERAL DESCRIPTION • Synchronous Operation. • 2 Stage Pipelined operation with 4 Burst • On-Chip Address Counter. • Self-Timed Write Cycle. • On- Chip Address and Control Registers.

Contextual Info: Preliminary KM736V599A/L 32Kx36 Synchronous SRAM 32K X 36 - Bit Synchronous Pipelined Burst SRAM FEATURES GENERAL DESCRIPTION • Synchronous Operation. • 2 Stage Pipelined operation with 4 Burst • On-Chip Address Counter. • Self-Timed Write Cycle. • On- Chip Address and Control Registers.

Contextual Info: SGS-THOMSON llD»[i[LI« M [](§S M48T559Y 64Kb (8K X 8 TIMEKEEPER SRAM with ADDRESS/DATA MULTIPLEXED • SOFTWARE and HARDWARE RESET for WATCHDOG TIMER ■ REGISTER COMPATIBLE with M48T59 TIMEKEEPER SRAM SNAPH AT (SH) Battery/Crystal ■ ADDRESS/DATA MULTIPLEXED I/O PINS

Contextual Info: 5 7 . SGS-THOMSON KfflD ®ltl !MM [)ïïD(ç^ M 48T559Y 64Kb (8K X 8) TIMEKEEPER® SRAM with ADDRESS/DATA MULTIPLEXED • SOFTWARE and HARDWARE RESET for WATCHDOG TIMER ■ REGISTER COMPATIBLE with M48T59 TIMEKEEPER SRAM SNAPHAT (SH) Battery/Crystal ■ ADDRESS/DATA MULTIPLEXED I/O PINS

Contextual Info: 32K x 32, 3.3V SYNCHRONOUS SRAM WITH 3.3V/2.5V PIPELINED OUTPUTS AND INTERLEAVED/LINEAR BURST COUNTER Integrated D evice Technology, Inc. FEATURES: PRELIMINARY IDT71V532 The 1DT71V532 SRAM contains write, data, address, and control registers. Internal logic allows the SRAM to generate

Contextual Info: 64K x 32, 3.3V SYNCHRONOUS SRAM WITH 3.3V/2.5V PIPELINED OUTPUTS AND INTERLEAVED/LINEAR BURST COUNTER Integrated Device Technology, Inc. FEATURES: PRELIMINARY IDT71V632 The ID T71V632 SRAM contains write, data, address, and control registers. Internal logic allows the SRAM to generate

K7A321800M

Abstract: K7A323600M
Contextual Info: K7A323600M K7A321800M PRELIMINARY 1Mx36 & 2Mx18 Synchronous SRAM 1Mx36 & 2Mx18-Bit Synchronous Pipelined Burst SRAM FEATURES GENERAL DESCRIPTION • • • • • • • Synchronous Operation. 2 Stage Pipelined operation with 4 Burst. On-Chip Address Counter.

Contextual Info: K7A323609M K7A321809M PRELIMINARY 1Mx36 & 2Mx18 Synchronous SRAM 1Mx36 & 2Mx18-Bit Synchronous Pipelined Burst SRAM FEATURES GENERAL DESCRIPTION • • • • • • • Synchronous Operation. 2 Stage Pipelined operation with 4 Burst. On-Chip Address Counter.

SRAM512KX36

Contextual Info: K7A163609A K7A161809A PRELIMINARY 512Kx36 & 1Mx18 Synchronous SRAM 512Kx36 & 1Mx18-Bit Synchronous Pipelined Burst SRAM FEATURES GENERAL DESCRIPTION • • • • • • • Synchronous Operation. 2 Stage Pipelined operation with 4 Burst. On-Chip Address Counter.

2930L

Abstract: SRAM512KX36
Contextual Info: K7A163608A K7A161808A PRELIMINARY 512Kx36 & 1Mx18 Synchronous SRAM 512Kx36 & 1Mx18-Bit Synchronous Pipelined Burst SRAM FEATURES GENERAL DESCRIPTION • Synchronous Operation. • 2 Stage Pipelined operation with 4 Burst. • On-Chip Address Counter. • Self-Timed Write Cycle.

Contextual Info: K7A323608M K7A321808M PRELIMINARY 1Mx36 & 2Mx18 Synchronous SRAM 1Mx36 & 2Mx18-Bit Synchronous Pipelined Burst SRAM FEATURES GENERAL DESCRIPTION • Synchronous Operation. • 2 Stage Pipelined operation with 4 Burst. • On-Chip Address Counter. • Self-Timed Write Cycle.

2930L

Abstract: K7A161801A K7A163601A
Contextual Info: K7A163601A K7A161801A PRELIMINARY 512Kx36 & 1Mx18 Synchronous SRAM 512Kx36 & 1Mx18-Bit Synchronous Pipelined Burst SRAM FEATURES GENERAL DESCRIPTION • Synchronous Operation. • 2 Stage Pipelined operation with 4 Burst. • On-Chip Address Counter. • Self-Timed Write Cycle.

K7A321801M

Abstract: K7A323601M
Contextual Info: K7A323601M K7A321801M PRELIMINARY 1Mx36 & 2Mx18 Synchronous SRAM 1Mx36 & 2Mx18-Bit Synchronous Pipelined Burst SRAM FEATURES GENERAL DESCRIPTION • Synchronous Operation. • 2 Stage Pipelined operation with 4 Burst. • On-Chip Address Counter. • Self-Timed Write Cycle.

Contextual Info: 64K 8K x8 TIMEKEEPER SRAM with ADDRESS/DATA MULTIPLEXED • SOFTWARE and HARDWARE RESET for WATCHDOG TIMER > REGISTER COMPATIBLE with M48T59 TIM EKEEPERSRAM ■ ADDRESS/DATA MULTIPLEXED I/O PINS ■ WATCHDOG TIMER - MONITORS OUT of CONTROL PROCESSOR or HUNG BUS

Contextual Info: 64K 8K x8 TIMEKEEPER SRAM with ADDRESS/DATA MULTIPLEXED • SOFTWARE and HARDWARE RESET for WATCHDOG TIMER > REGISTER COMPATIBLE with M48T59 TIM EKEEPERSRAM ■ ADDRESS/DATA MULTIPLEXED I/O PINS ■ WATCHDOG TIMER - MONITORS OUT of CONTROL PROCESSOR or HUNG BUS

Contextual Info: KM716V689 64Kx16 Synchronous SRAM 64K X 16-Bit Synchronous Pipelined Burst SRAM FEATURES GENERAL DESCRIPTION • Synchronous Operation. The KM716V689 is a 1,048,576-bit Synchronous Static • 2 Stage Pipelined operation with 4 Burst Random • On-Chip Address Counter.

Contextual Info: /= 7 SGS-THOMSON * 7 # . MO g[iSmi(STO li*I M48T558 ADDRESS/DATA MULTIPLEXED 8Kx 8 TIMEKEEPER SRAM PRODUCT PREVIEW • REGISTER COMPATIBLE with M48T58and M48T18 TIMEKEEPER SRAM ■ ADDREES/DATA MULTIPLEXED I/O PINS ■ INTEGRATED ULTRA LOW POWER SRAM, REALTIME CLOCK, POWER-FAILCONTROL

Contextual Info: GS820E32AT-180/166/133/4/5 64K x 32 2Mb Synchronous Burst SRAM Functional Description tin Applications The GS820E32A is a 2,097,152-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache