aa11
Abstract: marking A00
Text: ADVANCE INFORMATION GALVANTECH, INC. GVT71512D36 512K X 36 SYNCHRONOUS BURST SRAM SYNCHRONOUS BURST SRAM PIPELINED OUTPUT 512K x 36 SRAM +3.3V SUPPLY, FULLY REGISTERED INPUTS AND OUTPUTS, BURST COUNTER FEATURES GENERAL DESCRIPTION • • • • • The Galvantech Synchronous Burst SRAM family
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GVT71512D36
GVT71512D36
288x36
aa11
marking A00
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PDF
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100-PIN
Abstract: GVT71256ZC36 GVT71512ZC18
Text: ADVANCE INFORMATION GVT71512ZC36/GVT71A24ZC18 512K X 36/1M X 18 ZBL SRAM GALVANTECH, INC. SYNCHRONOUS ZBL SRAM PIPELINED OUTPUT 512K x 36 SRAM 1M x 18 SRAM +3.3V SUPPLY, +3.3V or +2.5V I/O FEATURES GENERAL DESCRIPTION • The GVT71512ZC36 and GVT71A24ZC18 SRAMs are
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GVT71512ZC36/GVT71A24ZC18
36/1M
GVT71512ZC36
GVT71A24ZC18
288x36
576x18
71512ZC36
71A24ZC18
100-PIN
GVT71256ZC36
GVT71512ZC18
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PDF
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100-PIN
Abstract: GVT71256ZB36 GVT71512ZB18 4g81
Text: PRELIMINARY GVT71256ZB36/GVT71512ZB18 256K X 36/512K X 18 ZBL SRAM GALVANTECH, INC. SYNCHRONOUS 256K x 36 SRAM ZBL SRAM 512K x 18 SRAM FLOW-THRU OUTPUT +3.3V SUPPLY, +3.3V or +2.5V I/O FEATURES • • • • • • • • • • • • • • • Zero Bus Latency, no dead cycles between write and read
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GVT71256ZB36/GVT71512ZB18
36/512K
100MHz
capabi36/GVT71512ZB18
71256ZB36
access/10ns
71512ZB18
100-PIN
GVT71256ZB36
GVT71512ZB18
4g81
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PDF
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Untitled
Abstract: No abstract text available
Text: LP62S4096F-T Series Preliminary 512K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 512K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 0.0 PRELIMINARY History Issue Date Remark Initial issue June 6, 2006 Preliminary June, 2006, Version 0.0 AMIC Technology, Corp.
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LP62S4096F-T
MO192
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PDF
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Untitled
Abstract: No abstract text available
Text: LP62S4096F-I Series Preliminary 512K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 512K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 0.0 PRELIMINARY History Issue Date Remark Initial issue June 6, 2006 Preliminary June, 2006, Version 0.0 AMIC Technology, Corp.
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LP62S4096F-I
MO192
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PDF
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LP62S4096E-T
Abstract: LP62S4096EV-55LLT LP62S4096EX-55LLT
Text: LP62S4096E-T Series 512K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 512K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 2.0 History Issue Date Remark Change VCCmax from 3.3V to 3.6V January 25, 2002 Final Add product family and 55ns specification
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LP62S4096E-T
32-pin
MO192
LP62S4096EV-55LLT
LP62S4096EX-55LLT
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PDF
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LP62S4096EX-70LLTF
Abstract: tvr 1024 LP62S4096E-T LP62S4096EU-55LLT LP62S4096EU-55LLTF LP62S4096EX-55LLTF
Text: LP62S4096E-T Series 512K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 512K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 2.0 History Issue Date Remark Change VCCmax from 3.3V to 3.6V January 25, 2002 Final Add product family and 55ns specification
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Original
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LP62S4096E-T
32-pin
MO192
LP62S4096EX-70LLTF
tvr 1024
LP62S4096EU-55LLT
LP62S4096EU-55LLTF
LP62S4096EX-55LLTF
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PDF
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as6c4008-55PCN
Abstract: as6c4008-55sin as6c4008-55 AS6C4008 as6c4008-55p 55pcn
Text: OCTOBER January 20072007 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM 512K X 8 BIT LOW POWER CMOS SRAM FEATURES GENERAL DESCRIPTION Access time : 55 ns Low power consumption: Operatingcurrent : 30/20mA TYP. Standby current : 4 µA (TYP.) C-version Single 2.7V ~ 5.5V power supply
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AS6C4008
30/20mA
32-pin
36-ball
AS6C4008
304-bit
as6c4008-55PCN
as6c4008-55sin
as6c4008-55
as6c4008-55p
55pcn
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PDF
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A62S9308
Abstract: No abstract text available
Text: A62S9308 Series Preliminary 512K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 512K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 0.0 PRELIMINARY History Issue Date Remark Initial issue February 12, 2001 Preliminary February, 2001, Version 0.0 AMIC Technology, Inc.
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A62S9308
A62S9308-S
A62S9308-SI
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PDF
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LP62S4096EV-70LLTF
Abstract: LP62S4096E-T LP62S4096EV-55LLT LP62S4096EV-55LLTF LP62S4096EX-70LLTF lp62s4096eu-70lltf
Text: LP62S4096E-T Series 512K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 512K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 2.0 History Issue Date Remark Change VCCmax from 3.3V to 3.6V January 25, 2002 Final Add product family and 55ns specification
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Original
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LP62S4096E-T
32-pin
MO192
LP62S4096EV-70LLTF
LP62S4096EV-55LLT
LP62S4096EV-55LLTF
LP62S4096EX-70LLTF
lp62s4096eu-70lltf
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PDF
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LP62S4096E-I
Abstract: LP62S4096EV-55LLI
Text: LP62S4096E-I Series 512K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 512K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 2.0 History Issue Date Remark Change VCCmax from 3.3V to 3.6V January 25, 2002 Final Add product family and 55ns specification
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LP62S4096E-I
32-pin
MO192
LP62S4096EV-55LLI
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PDF
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Untitled
Abstract: No abstract text available
Text: LP62S4096F-I Series 512K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 512K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History History Issue Date 0.0 Initial issue June 6, 2006 Preliminary 1.0 Final version release March 6, 2007 Final Rev. No. March, 2007, Version 1.0
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LP62S4096F-I
32-pin
36-bNE
MO192
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PDF
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LP62S4096E-I
Abstract: LP62S4096EU-55LLI
Text: LP62S4096E-I Series 512K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 512K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 2.0 History Issue Date Remark Change VCCmax from 3.3V to 3.6V January 25, 2002 Final Add product family and 55ns specification
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Original
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LP62S4096E-I
32-pin
MO192
LP62S4096EU-55LLI
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PDF
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AS6C4008-55PCN
Abstract: AS6C4008 AS6C4008-55SIN AS6C4008-55TIN AS6C4008-55
Text: January 20072007 February AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM 512K X 8 BIT LOW POWER CMOS SRAM FEATURES GENERAL DESCRIPTION Access time : 55 ns Low power consumption: Operatingcurrent : 30/20mA TYP. Standby current : 4 µA (TYP.) C-version Single 2.7V ~ 5.5V power supply
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AS6C4008
30/20mA
32-pin
36-ball
44-pin
AS6C4008
304-bit
AS6C4008-55PCN
AS6C4008-55SIN
AS6C4008-55TIN
AS6C4008-55
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LP62S4096E-T
Abstract: LP62S4096EU-55LLT LP62S4096EV-55LLT LP62S4096EX-55LLT
Text: LP62S4096E-T Series 512K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 512K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 2.0 History Issue Date Change VCCmax from 3.3V to 3.6V January 25, 2002 Remark Add product family and 55ns specification January, 2002, Version 2.0
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LP62S4096E-T
MO192
LP62S4096EU-55LLT
LP62S4096EV-55LLT
LP62S4096EX-55LLT
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PDF
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LP62S4096E-I
Abstract: LP62S4096EV-55LLI LP62S4096EX-55LLI
Text: LP62S4096E-I Series 512K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 512K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 2.0 History Issue Date Remark Change VCCmax from 3.3V to 3.6V January 25, 2002 Final Add product family and 55ns specification
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Original
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LP62S4096E-I
32-pin
MO192
LP62S4096EV-55LLI
LP62S4096EX-55LLI
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PDF
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Untitled
Abstract: No abstract text available
Text: January 2007 February 2007 AS6C4008 512K X 8 BIT LOW POWER CMOS SRAM 512K X 8 BIT LOW POWER CMOS SRAM FEATURES GENERAL DESCRIPTION Access time : 55 ns Low power consumption: Operatingcurrent : 30/20mA TYP. Standby current : 4 µA (TYP.) C-version Single 2.7V ~ 5.5V power supply
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AS6C4008
30/20mA
32-pin
32-pin
36-ball
AS6C4008
304-bit
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PDF
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LP62S4096EU-55LLTF
Abstract: No abstract text available
Text: LP62S4096E-T Series 512K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 512K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 2.0 History Issue Date Remark Change VCCmax from 3.3V to 3.6V January 25, 2002 Final Add product family and 55ns specification
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Original
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LP62S4096E-T
32-pin
MO192
LP62S4096EU-55LLTF
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PDF
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Untitled
Abstract: No abstract text available
Text: LP62S4096E-I Series 512K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 512K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 2.0 History Issue Date Remark Change VCCmax from 3.3V to 3.6V January 25, 2002 Final Add product family and 55ns specification
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Original
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LP62S4096E-I
32-pin
MO192
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PDF
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Untitled
Abstract: No abstract text available
Text: LP62S4096F-T Series Preliminary 512K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 512K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 0.0 0.1 PRELIMINARY History Initial issue Change temperature from 0°C-70°C to -10°C-70°C November, 2006, Version 0.1
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Original
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LP62S4096F-T
MO192
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PDF
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LP62S4096E-I
Abstract: LP62S4096EU-55LLI LP62S4096EV-55LLI LP62S4096EX-55LLI
Text: LP62S4096E-I Series 512K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 512K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 2.0 History Issue Date Remark Change VCCmax from 3.3V to 3.6V January 25, 2002 Add product family and 55ns specification January, 2002, Version 2.0
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Original
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LP62S4096E-I
MO192
LP62S4096EU-55LLI
LP62S4096EV-55LLI
LP62S4096EX-55LLI
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PDF
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LP62S4096FX-70LLTF
Abstract: No abstract text available
Text: LP62S4096F-T Series 512K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 512K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 0.0 0.1 1.0 History Remark Preliminary Change temperature from 0°C-70°C to -10°C-70°C Issue Date June 6, 2006 November 17, 2006
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LP62S4096F-T
MO192
LP62S4096FX-70LLTF
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PDF
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CY7C13201KV18
Abstract: CY7C13201KV18-300BZXC cy7c13201
Text: CY7C13201KV18 18-Mbit DDR II SRAM 2-Word Burst Architecture Features Functional Description • 18 Mbit Density 512K x 36 The CY7C13201KV18 is 1.8V Synchronous Pipelined SRAM equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and
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CY7C13201KV18
18-Mbit
CY7C13201KV18
36-bit
CY7C13201KV18-300BZXC
cy7c13201
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PDF
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Untitled
Abstract: No abstract text available
Text: ADVANCE MICRON8 I 8Mb: 512K x 18, 256K x 32/36 PIPELINED, DCD SYNCBURST SRAM TEOWOLOOV, INC. MT58L512L18D, MT58L256L32D, MT58L256L36D; MT58L512V18D, MT58L256V32D, MT58L256V36D 8Mb SYNCBURST SRAM 3.3V Supply, 3.3V or 2.5V I/O, Pipelined, Double-Cycle Deselect
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OCR Scan
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MT58L512L18D,
MT58L256L32D,
MT58L256L36D;
MT58L512V18D,
MT58L256V32D,
MT58L256V36D
MT58L512L18D
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PDF
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