SRAM 2M Search Results

UT8R2M39

Abstract: UT8R4M39 UT8R1M39
Contextual Info: Standard Products UT8R1M39 40Megabit SRAM MCM UT8R2M39 80Megabit SRAM MCM UT8R4M39 160Megabit SRAM MCM Data Sheet January 2013 www.aeroflex.com/memories INTRODUCTION FEATURES  20ns Read, 10ns Write maximum access times available  Functionally compatible with traditional 1M, 2M, or 4M x

Contextual Info: Standard Products UT8ER1M32 32Megabit SRAM MCM UT8ER2M32 64Megabit SRAM MCM UT8ER4M32 128Megabit SRAM MCM Preliminary Data Sheet August 28, 2012 www.aeroflex.com/memories FEATURES  20ns Read, 10ns Write maximum access times available  Functionally compatible with traditional 1M, 2M and 4M

32-KW Load Bank

Abstract: tes 1310 LFBGA 555H SST34HF324G
Contextual Info: 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory SST34HF324G SST34HF324G32Mb Dual-Bank Flash + 4 Mb SRAM MCP ComboMemory Data Sheet FEATURES: • Flash Organization: 2M x16 – 32 Mbit: 24Mbit + 8Mbit • Concurrent Operation – Read from or Write to SRAM while

GVT71256T18

Abstract: DQ974
Contextual Info: ADVANCE INFORMATION GALVANTECH, INC. SYNCHRONOUS CACHE TAG SRAM PIPELINED OUTPUT GVT71256T18 256K X 18 SYNCHRONOUS TAG SRAM 256K x 18 SRAM +3.3V SUPPLY WITH CLOCKED REGISTERED INPUTS FEATURES GENERAL DESCRIPTION • • • • • • The Galvantech Synchronous Burst SRAM family

Contextual Info: CYM1471 CYM1481 CYPRESS SEMICONDUCTOR 1024K X 8 SRAM Module 2048K X 8 SRAM Module Features Functional Description • High-density 8-/16-megabit SRAM modules • High-speed CMOS SRAMs — Access time of 85 ns • Low active power — 605 mVY max. , 2M x 8

68S16000

Abstract: AB-020
Contextual Info: 512K x 32 SRAM MODULE PUMA 68S16000/AB-020/025/35/45 Issue 5.0 : May 2001 • User Configurable as 8 / 16 / 32 bit wide output. • Operating Power : • Standby Power : CMOS • Single 5V±10% Power supply. 512K x 8 SRAM 512K x 8 SRAM 512K x 8 SRAM CS1

Contextual Info: CY7C1329H 2-Mbit 64 K x 32 Pipelined Sync SRAM 2-Mbit (64 K × 32) Pipelined Sync SRAM Features Functional Description • Registered inputs and outputs for pipelined operation The CY7C1329H SRAM integrates 64 K × 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter

123D

Abstract: AS5SS128K36
Contextual Info: SRAM Austin Semiconductor, Inc. GENERAL DESCRIPTION 128K x 36 SSRAM The Austin Semiconductor, Inc. Zero Bus Latency SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. ASI’s 4Mb ZBL SRAMs integrate a 128K x 36 SRAM core

Contextual Info: K7A323608M K7A321808M PRELIMINARY 1Mx36 & 2Mx18 Synchronous SRAM 1Mx36 & 2Mx18-Bit Synchronous Pipelined Burst SRAM FEATURES GENERAL DESCRIPTION • Synchronous Operation. • 2 Stage Pipelined operation with 4 Burst. • On-Chip Address Counter. • Self-Timed Write Cycle.

MT58L64L36P

Abstract: MS-026 MT58L128L18P MT58L128V18P MT58L64L32P MT58L64V32P MT58L64V36P
Contextual Info: NOT RECOMENDED FOR NEW DESIGNS 2Mb: 128K x 18, 64K x 32/36 PIPELINED, SCD SYNCBURST SRAM 2Mb SYNCBURST SRAM MT58L128L18P, MT58L64L32P, MT58L64L36P; MT58L128V18P, MT58L64V32P, MT58L64V36P 3.3V VDD, 3.3V or 2.5V I/O, Pipelined, SingleCycle Deselect FEATURES

Contextual Info: 2Mb: 128K x 18, 64K x 32/36 PIPELINED, SCD SYNCBURST SRAM MT58L128L18P, MT58L64L32P, MT58L64L36P; MT58L128V18P, MT58L64V32P, MT58L64V36P 2Mb SYNCBURST SRAM 3.3V Vdd, 3.3V or 2.5V I/O, Pipelined, Single-Cycle Deselect FEATURES • Fast clock and OE# access times

intel 8082

Abstract: MT58L128L18PT-10 MS-026 MT58L128L18P MT58L128V18P MT58L64L32P MT58L64L36P MT58L64V32P MT58L64V36P bsram
Contextual Info: 2Mb: 128K x 18, 64K x 32/36 PIPELINED, SCD SYNCBURST SRAM 2Mb SYNCBURST SRAM MT58L128L18P, MT58L64L32P, MT58L64L36P; MT58L128V18P, MT58L64V32P, MT58L64V36P 3.3V VDD, 3.3V or 2.5V I/O, Pipelined, SingleCycle Deselect FEATURES • Fast clock and OE# access times

13001 B 8D

Abstract: 13001 s 8d 13001 s 6d 13001 c 6h mt58l64l36p 13001 8d
Contextual Info: 2Mb: 128K x 18, 64K x 32/36 PIPELINED, SCD SYNCBURST SRAM 2Mb SYNCBURST SRAM MT58L128L18P, MT58L64L32P, MT58L64L36P; MT58L128V18P, MT58L64V32P, MT58L64V36P 3.3V VDD, 3.3V or 2.5V I/O, Pipelined, SingleCycle Deselect FEATURES • Fast clock and OE# access times

mt58l64l36p

Contextual Info: 2Mb: 128K x 18, 64K x 32/36 PIPELINED, SCD SYNCBURST SRAM MT58L128L18P, MT58L64L32P, MT58L64L36P; MT58L128V18P, MT58L64V32P, MT58L64V36P 2Mb SYNCBURST SRAM 3.3V VDD, 3.3V or 2.5V I/O, Pipelined, Single-Cycle Deselect FEATURES • Fast clock and OE# access times

MR2A16AC

Abstract: tsop 48 PIN type2 MR2A16AMY MRAM MR2A16ACYS35R 44TSOP mr2a16amys35 MR2A16ATS35 MR2A16A 012MAX
Contextual Info: MR2A16A FEATURES 256K x 16 MRAM Memory • Fast 35 ns Read/Write Cycle • SRAM Compatible Timing, Uses Existing SRAM Controllers Without Redesign • Unlimited Read & Write Endurance • Data Non-volatile for >20-years at Temperature • One Memory Replaces Flash, SRAM, EEPROM and BBSRAM in

Contextual Info: ADVANCE MT58LC128K32/36F1 128K X 32/36 SYNCBURST SRAM MICRON I TECHNOLOGY, INC. 128K x 32/36 SRAM SYNCHRONOUS SRAM +3.3V SUPPLY, +2.5V I/O, PIPELINED AND SELECTABLE BURST MODE FEATURES • • • • • • • • • • • • • • • • • •

K7A323600M

Abstract: K7B321825M-QC65 K7A321800M
Contextual Info: K7A323600M K7A321800M 1Mx36 & 2Mx18 Synchronous SRAM Document Title 1Mx36 & 2Mx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial draft May. 10. 2001 Advance 0.1 1. Add 165FBGA package Aug. 29. 2001 Preliminary

MR2A08AMYS35

Abstract: AECQ-100 MR2A08AYS35 BGA 8 x 8 tray MR2A08A
Contextual Info: MR2A08A FEATURES 512K x 8 MRAM Memory • Fast 35ns Read/Write Cycle • SRAM Compatible Timing, Uses Existing SRAM Controllers Without Redesign • Unlimited Read & Write Endurance • Data Always Non-volatile for >20-years at Temperature • One Memory Replaces Flash, SRAM, EEPROM and BBSRAM in

Contextual Info: 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM 2Mb SYNCBURST SRAM MT58L128L18F, MT58L64L32F, MT58L64L36F; MT58L128V18F, MT58L64V32F, MT58L64V36F 3.3V VDD, 3.3V or 2.5V I/O, Flow-Through FEATURES 100-Pin TQFP* • Fast clock and OE# access times

MC-22002

Contextual Info: PRELIMINARY DATA SHEET_ MOS INTEGRATED CIRCUIT MC-22002 MCP MULTI-CHIP PACKAGE FLASH MEMORY AND SRAM 8M-BIT FLASH MEMORY AND 2M-BIT SRAM Description The MC-22002 is a MCP (Multi-Chip Package) of8,388,608 bits (Byte mode :1,048,576 words by 8 bits, W ord

Contextual Info: PRELIMINARY DATA SHEET_ MOS INTEGRATED CIRCUIT MC-22000 MCP MULTI-CHIP PACKAGE FLASH MEMORY AND SRAM 8M-BIT FLASH MEMORY AND 2M-BIT SRAM Description The MC-22000 is a MCP (Multi-Chip Package) of 8,388,608 bits (1,048,576 words by 8 bits) flash memory and

pa 66 gf

Abstract: M36W432BG M36W432TG AI07927 PA 6.6 GF 13
Contextual Info: M36W432TG M36W432BG 32 Mbit 2Mb x16, Boot Block Flash Memory and 4 Mbit (256Kb x16) SRAM, Multiple Memory Product PRELIMINARY DATA FEATURES SUMMARY • MULTIPLE MEMORY PRODUCT – 32 Mbit (2Mb x 16), Boot Block, Flash Memory – 4 Mbit (256Kb x 16) SRAM Memory

K7A321801M

Abstract: K7A323601M
Contextual Info: K7A323601M K7A321801M PRELIMINARY 1Mx36 & 2Mx18 Synchronous SRAM Document Title 1Mx36 & 2Mx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial draft May. 10. 2001 Preliminary 0.1 1. Speed bin merge. From K7A3236 18 08M to K7A3236(18)01M.

555H

Abstract: BKX555H SST34HF3244C
Contextual Info: 32 Mbit Concurrent SuperFlash + 4 Mbit SRAM ComboMemory SST34HF3244C SST34HF32x4x32Mb CSF + 4/8/16 Mb SRAM x16 MCP ComboMemory Data Sheet FEATURES: • Flash Organization: 2M x16 or 4M x8 • Dual-Bank Architecture for Concurrent Read/Write Operation – 32 Mbit Top Sector Protection