SPARTAN3 Search Results

SPARTAN3 Datasheets (6)

Part	Manufacturer	Description	Datasheet Type	PDF
Spartan-3	Xilinx	Field Programmable Gate Array	Original	PDF
Spartan-3	Xilinx	Spartan-3 FPGA Family: Introduction and Ordering Information	Original	PDF
Spartan-3	Xilinx	Spartan-3 FPGA Family: Complete Data Sheet	Original	PDF
Spartan-3	Xilinx	Spartan-3 FPGA Family: DC and Switching Characteristics	Original	PDF
Spartan-3	Xilinx	Spartan-3 Automotive XA FPGA	Original	PDF
Spartan-3L	Xilinx	Low Power FPGA Family	Original	PDF

SPARTAN3 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
xilinx uart verilog code for spartan 3a Abstract: UG332 HW-SPAR3AN-SK-UNI-G kcpsm3 picoblaze CRC-16 and verilog picoblaze kcpsm3 3S200AN 3S700AN xc3s200an Text: Application Note: Extended Spartan-3A Family R Fail-safe MultiBoot Reference Design Author: Jim Wesselkamper XAPP468 v1.0 November 4, 2008 Summary Introduction This application note describes a reference design that adds fail-safe mechanisms to the MultiBoot capabilities of the Extended Spartan -3A family of FPGAs (Spartan-3A, Spartan3AN, and Spartan-3A DSP platforms). The reference design configures specific FPGA logic via	Original	XAPP468 xilinx uart verilog code for spartan 3a UG332 HW-SPAR3AN-SK-UNI-G kcpsm3 picoblaze CRC-16 and verilog picoblaze kcpsm3 3S200AN 3S700AN xc3s200an	PDF
TB-3S-1600E Abstract: inrevium TP21-TP27 XC3S1600E-4FG484C ELPIDA DDR User XCF08PVO48 EDD5116ADTA-6B-E ICS8430-61 M25P16-VMF6P 3S1600E Text: http://inrevium.teldevice.co.jp/ TB-3S-1600E SPARTAN3E Evaluation Board TB-3S-1600E Hardware User’s Guide Rev1.1 1, Higashi-Katacho, Tsuzuki-ku Yokohama-City, Kanagawa, Japan 224-0045 TEL: +81-45-474-7028 FAX: +81-45-474-5583 E-mail: x2marketing@teldevice.co.jp	Original	TB-3S-1600E TB-3S-1600E inrevium TP21-TP27 XC3S1600E-4FG484C ELPIDA DDR User XCF08PVO48 EDD5116ADTA-6B-E ICS8430-61 M25P16-VMF6P 3S1600E	PDF
intel batch MARKING flash Abstract: spi flash spartan 6 intel batch MARKING date code marking intel strataflash intel nor flash Intel StrataFlash Parallel NOR Flash PROM XAPP1106 flash memory application image processing using xilinx platform studio SPARTAN-3A DSP 1800A Text: Application Note: Embedded Processing R XAPP1106 v1.2 January 27, 2009 Using and Creating Flash Files for the MicroBlaze Development Kit - Spartan3A DSP 1800A Starter Platform Author: Sundararajan Ananthakrishnan/Casey Cain Abstract This application note describes the files for programming the serial Flash memory and the	Original	XAPP1106 intel batch MARKING flash spi flash spartan 6 intel batch MARKING date code marking intel strataflash intel nor flash Intel StrataFlash Parallel NOR Flash PROM XAPP1106 flash memory application image processing using xilinx platform studio SPARTAN-3A DSP 1800A	PDF
Video sync splitter lm Abstract: sdi to hdmi converter ic hd-SDI splitter hdmi CONVERTER SDI IC Current-Mode PWM Controller 6-SOIC 555 timer SPICE model video sdi splitter catalog 4000 single family smd cmos ypbpr video splitter smd code FX mosfet Text: Professional and Broadcast Video Solutions Guide www.national.com/sdi 2009 Vol. 1 SDI Solutions SerDes Solutions Clock and Timing Solutions Analog Video Solutions Audio Solutions Power Solutions Design Resources 84 Enabling Energy Efficiency Through PowerWise Video Solutions	Original		PDF
XC3S700A Abstract: xc3s200aft256 XC3S400AFT256 XC3S50A L01P L02P FG320 UG331 L05P xc3s400a ftg256 Text: Spartan-3A FPGA Family: Data Sheet R DS529 July 10, 2007 Product Specification Module 1: Introduction and Ordering Information - DS529-1 v1.4.1 July 10, 2007 • • • • • • • Introduction Features Architectural and Configuration Overview General I/O Capabilities	Original	DS529 DS529-1 DS529-2 DS529-3 XC3S50A XC3S200A FT256 DS529-4 XC3S700A xc3s200aft256 XC3S400AFT256 L01P L02P FG320 UG331 L05P xc3s400a ftg256	PDF
3S400 Abstract: 3S200 visionprobe 2V250 V600 3S50 3S400 ibis DIAB ISE BASEX MXE Text: Devices Design Entry Embedded System Design Synthesis Feature ISE WebPACK ISE BaseX ISE Foundation ISE Alliance Virtex Series Virtex-E: V50E -V300E Virtex-II: 2V40 - 2V250 Virtex-II Pro: 2VP2 Virtex: V50 - V600 Virtex-E: V50E - V600E Virtex-II: 2V40 - 2V500	Original	-V300E 2V250 V600E 2V500 XC2S400E XC2S600E) 3S200, 3S400 3S400 3S200 visionprobe 2V250 V600 3S50 3S400 ibis DIAB ISE BASEX MXE	PDF
AC307 Abstract: SPARTAN 3E STARTER BOARD L262144 memory 2114 XILINX/SPARTAN 3E STARTER BOARD AFS090 generic SPI AFS-EVAL Text: Application Note AC307 Configuring SRAM FPGAs Using Actel Fusion Introduction Due to the nature of SRAM technology, SRAM-based FPGAs are volatile and lose their configuration when powered off, so they must be reconfigured at every power-up. Hence, almost every system using SRAMbased FPGAs contains an additional nonvolatile memory, such as flash PROM or EEPROM, to store the	Original	AC307 AC307 SPARTAN 3E STARTER BOARD L262144 memory 2114 XILINX/SPARTAN 3E STARTER BOARD AFS090 generic SPI AFS-EVAL	PDF
socket am3 pinout Abstract: socket AM2 pinout AM2 pinout Socket F am2 socket pin diagram am3 socket pinout am3 socket pin diagram am2 socket pinout socket AM3 pinout diagram PCIe cable pinout LX5511 Text: Broaddown4 User Manual Issue – 2.00 draft Enterpoint Ltd. - Broaddown4 Manual – Issue 2.00 11/04/2007 Kit Contents You should receive the following items with you Broaddown4 development kit: 1 - Broaddown4 Board 2 - Programming Cable Prog2 Figure 1 - Broaddown4 Board	Original		PDF
XC3S700A-FG484 Abstract: XC3S700AFG484 MT47H32M16BN-3 MT47H32M16 LCD with picoblaze MT47H32M16BN MT47H32M16XX-5E T-2420 T2420 Thermonics T 2420 Text: Application Note: Spartan-3A FPGA Family Implementing DDR2-400 Memory Interfaces in Spartan-3A FPGAs R Author: Eric Crabill XAPP458 v1.0.1 July 9, 2009 Summary High-performance consumer products and their requirement for low-cost, high-bandwidth memory create demand for high-performance DDR2 memory interfaces. Xilinx offers a	Original	DDR2-400 XAPP458 XC3S700A-FG484 XC3S700AFG484 MT47H32M16BN-3 MT47H32M16 LCD with picoblaze MT47H32M16BN MT47H32M16XX-5E T-2420 T2420 Thermonics T 2420	PDF
C3202 Abstract: C32025 TMS320C25 test bench for 16 bit shifter C32025TX Text: Control Unit o 16-bit instruction decoding o Repeat instructions for effi- C32025 Digital Signal Processor Core cient use of program space and enhanced execution Central Arithmetic-Logic Unit o 16-bit parallel shifter; 32-bit arithmetic and logical operations	Original	16-bit C32025 32-bit C32025 TMS320C25 C3202 test bench for 16 bit shifter C32025TX	PDF
Untitled Abstract: No abstract text available Text: Spartan-6 FPGA Clocking Resources User Guide UG382 v1.8 June 20, 2013 Notice of Disclaimer The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL	Original	UG382	PDF
XAPP1014 Abstract: smpte 424m to smpte 274m 3G-SDI serializer XAPP224 DATA RECOVERY 425M SMPTE-305M PCIe BT.656 ML571 vhdl code for multiplexing Tables in dvb-t SONY service manual circuits Text: Audio/Video Connectivity Solutions for Virtex-5 FPGAs Reference Designs for the Broadcast Industry: Volume 2 XAPP1014 v1.2 November 9, 2009 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development	Original	XAPP1014 XAPP1014 smpte 424m to smpte 274m 3G-SDI serializer XAPP224 DATA RECOVERY 425M SMPTE-305M PCIe BT.656 ML571 vhdl code for multiplexing Tables in dvb-t SONY service manual circuits	PDF
verilog code for implementation of des Abstract: 3S1200E-4 verilog code for des Text: FIPS 46-3 Standard Compliant DES Data Encryption Standard Core Encryption/Decryption performed in 16 cycles ECB mode 56 bits of security For use in FPGA or ASIC designs Verilog IP Core Non Pipelined version Small gate count The DES core implements the Data Encryption Standard (DES) documented in the U.S.	Original	0x0123456789abcdef 0x4e6f772069732074 0x68652074696d6520 0x666f7220616c6c20 0x3fa40e8a984d4815 0x6a271787ab8883f9 0x893d51ec4b563b53 verilog code for implementation of des 3S1200E-4 verilog code for des	PDF
6SLX25-2 Abstract: 3s1000-5 SPARTAN-6 image processing 3S100 DSP48A DSP48E 6SLX25 "motion jpeg" dcm verilog code Text: Baseline ISO/IEC 10918-1 JPEG Compliance Programmable Huffman Tables two DC, two AC and JPEG-D Programmable quantization tables (four) Baseline JPEG Decoder Core Up to four color components (optionally extendable to 255 components) Supports all possible scan configurations and all JPEG formats	Original	1920x1152, 6SLX25-2 3s1000-5 SPARTAN-6 image processing 3S100 DSP48A DSP48E 6SLX25 "motion jpeg" dcm verilog code	PDF

RAMB36E1 Abstract: RAMB16s spartan6 lx25 LX15-12 deinterlace RAM18E1 bob deinterlacer cpu 226 deinterlacer BT.656 Text: VDINT Basic BT.656 Video Deinterlacer IP Core This deinterlacer IP core converts a standard interlaced video stream to progressive video format for further processing or display. Extremely efficient, the deinterlacer core requires little area and transforms the video with practically no delay.	Original	480i/576i, RAMB36E1 RAMB16s spartan6 lx25 LX15-12 deinterlace RAM18E1 bob deinterlacer cpu 226 deinterlacer BT.656	PDF
philips RC5 protocol Abstract: rc5 protocol Manchester CODING DECODING FPGA philips RC5 decoder RC5 IR home theater IR remote control circuit diagram virtex 2 pro manchester encoder xilinx RC5 encoder RC5 philips Text: 5-bit address and 6-bit command length IR-RC5-E and -D Bi-phase coding also known as Manchester coding Infrared Encoder and Decoder Cores Carrier frequency of 36 kHz as per the RC5 standard Fully synchronous design Encoder Features This pair of cores implements an Encoder and a Decoder for Consumer IR (CIR) infrared remote control signals using the popular RC5 IR protocol, originally developed by	Original		PDF
6SLX150-2 Abstract: verilog code for dma controller synchronous fifo design in verilog interrupt controller verilog code 6SLX150 6VCX240-2 verilog hdl code for programmable peripheral interface Text: Full compliance with the USB 2.0 specification USBHS-DEV High Speed USB Device Controller Core The USBHS-DEV core implements a complete high/full-speed 480/12 Mbps peripheral controller that interfaces to a UTMI USB port transceiver on one side and to a system’s	Original		PDF
4VFX12-12 Abstract: No abstract text available Text: Complies with the USB 2.0 specification USBHS-HUB USB Hi-Speed Embedded Hub Controller Core The USBHS-HUB core implements a hi-speed configurable USB Hub controller that can serve as an interface between a USB host and multiple USB peripheral devices, each	Original		PDF
verilog coding using instantiations Abstract: DS512 XAPP917 Text: w Application Note: Migration Guide R Block Memory Generator Migration Guide XAPP917 v5.0 September 16, 2009 Summary This document provides step-by-step instructions for migrating designs containing instances of either the legacy memory cores (Dual Port Block Memory and Single Port Block Memory cores)	Original	XAPP917 verilog coding using instantiations DS512 XAPP917	PDF
SPARTAN-3 XC3S400 Abstract: CZ80CPU Z84C00 Text: CZ80CPU 8-Bit Microprocessor Core The CZ80CPU implements a fast, fully-functional, single-chip, 8-bit microprocessor with the same instruction set as the Z80. The core has a 16-bit address bus capable of directly accessing 64kB of memory space. It has 252 root instructions with the reserved 4 bytes as prefixes, and accesses	Original	CZ80CPU CZ80CPU 16-bit CZ80CHIP, SPARTAN-3 XC3S400 Z84C00	PDF
NEC protocol Abstract: NEC IR virtex 2 pro NEC protocol datasheet home theater IR remote control circuit diagram circuit diagram for simple IR receiver IR LED and photodiode pair Virtex4 XC4VFX60 Spartan 3E IR MODULE 3-8 decoder circuit diagram Text: 8-bit address and 8-bit command length IR-NEC-E and -D Carrier frequency of 38 kHz as per the NEC standard Infrared Encoder and Decoder Cores Pulse distance modulation This pair of cores implements an Encoder and a Decoder for Consumer IR CIR infrared remote control signals using the popular NEC IR protocol. The cores are available	Original		PDF
16750 UART texas instruments Abstract: 16750 UART uart 16750 H16750S uart 16750 baud rate Text: Capable of running all existing 16450 and 16550a software Fully Synchronous design. All inputs and outputs are based on the rising edge of clock H16750S UART with FIFOs, IrDA, and Synchronous CPU Interface Core The H16750S is a standard UART providing 100% software compatibility with the popular Texas Instruments 16750 device. It performs serial-to-parallel conversion on data	Original	16550a H16750S H16750S 16450-compatible 16750 UART texas instruments 16750 UART uart 16750 uart 16750 baud rate	PDF
verilog edge detection 2d filter xilinx Abstract: No abstract text available Text: RBBRC High Performance Raster-to-Block Block-to-Raster Converter Xilinx Core Digital image acquisition display devices, both static and video, produce (need) image samples on a line-by-line/pixel-by-pixel basis; a scheme well known as raster scan. On the other hand many image processing-transform algorithms work on a	Original		PDF
UG628 Abstract: No abstract text available Text: Spartan-6 FPGA Configuration User Guide UG380 v2.5 January 23, 2013 Notice of Disclaimer The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL	Original	UG380 UG628	PDF

SPARTAN3 Search Results

SPARTAN3 Datasheets (6)

SPARTAN3 Datasheets Context Search

xilinx uart verilog code for spartan 3a

TB-3S-1600E

intel batch MARKING flash

Video sync splitter lm

XC3S700A

3S400

AC307

socket am3 pinout

XC3S700A-FG484

C3202

Untitled

XAPP1014

verilog code for implementation of des

6SLX25-2

RAMB36E1

philips RC5 protocol

6SLX150-2

4VFX12-12

verilog coding using instantiations

SPARTAN-3 XC3S400

NEC protocol

16750 UART texas instruments

verilog edge detection 2d filter xilinx

UG628