SN74GTL Search Results

Contextual Info: SN54GTL1655, SN74GTL1655 16-BIT LVTTL TO GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS WITH LIVE INSERTION SCBS696C - JULY 1997 - REVISED MAY 1998 Members of the Texas Instruments Widebus Family SN74G TL1655 . . . DGG PACKAGE TOP VIEW Translate Between GTL/GTL+ Signal Level

Contextual Info: SN74GTLPH1645 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER www.ti.com FEATURES • • • • • • • • • • • • Member of the Texas Instruments Widebus Family TI-OPC™ Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC™ Circuitry Improves Signal Integrity and

Contextual Info: SN74GTLPH1616 17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS www.ti.com FEATURES • • • • • • • • • • • • • • • Member of the Texas Instruments Widebus Family UBT™ Transceiver Combines D-Type Latches

A115-A

Abstract: C101 SN74GTLP817 SN74GTLP817DW SN74GTLP817DWR
Contextual Info: SN74GTLP817 GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER SCES285C – OCTOBER 1999 – REVISED FEBRUARY 2001 D D D D D D D D D D D D DGV, DW, OR PW PACKAGE TOP VIEW OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP

Contextual Info: SN74GTLPH32916 34-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS www.ti.com SCES380A – JANUARY 2002 – REVISED JUNE 2005 FEATURES • • • • • • • • Member of the Texas Instruments Widebus+ Family UBT™ Transceiver Combines D-Type Latches

Contextual Info: www.ti.com SN74GTL16622A 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER SCBS673F – AUGUST 1996 – REVISED APRIL 2005 FEATURES • • • • • • • • • • Member of Texas Instruments Widebus Family OEC™ Circuitry Improves Signal Integrity and

Contextual Info: SN74GTLPH32912 36-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER www.ti.com FEATURES • • • • • • • Member of the Texas Instruments Widebus+ Family UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, and

A115-A

Abstract: C101 SN74GTLP1395 signal path designer
Contextual Info: www.ti.com SN74GTLP1395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY FEATURES • • • • • • • • • • • TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes

A115-A

Abstract: C101 SN74GTL2007 26LVTTL
Contextual Info: SN74GTL2007 12ĆBIT GTLĆ/GTL/GTL+ TO LVTTL TRANSLATOR SCLS609 − MARCH 2005 D Operates as a GTL-/GTL/GTL+ to LVTTL or D D D PW PACKAGE TOP VIEW LVTTL to GTL-/GTL/GTL+ Translator Series Termination on TTL Outputs of 30 W Latch-Up Testing Done to JEDEC Standard

Signal Path Designer

Contextual Info: SN74GTLP2033 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES352C – JUNE 2001 – REVISED SEPTEMBER 2001 D D D D D D D D D D D D D Member of the Texas Instruments Widebus Family TI-OPC Circuitry Limits Ringing on

Contextual Info: SN74GTLPH1645 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER www.ti.com FEATURES • • • • • • • • • • • • Member of the Texas Instruments Widebus Family TI-OPC™ Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC™ Circuitry Improves Signal Integrity and

A115-A

Abstract: C101 JESD-22 N2 SC70
Contextual Info: SN74GTL3004 www.ti.com . SCBS873A – FEBRUARY 2008 – REVISED APRIL 2008 SELECTABLE GTL VOLTAGE REFERENCE FEATURES

A115-A

Abstract: C101 SN74GTLPH16927 SN74GTLPH16927GR
Contextual Info: SN74GTLPH16927 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS www.ti.com SCES413 – OCTOBER 2002 – REVISED JUNE 2005 FEATURES • • • • • • • • • • • • • • DGG OR DGV PACKAGE TOP VIEW Member of the Texas Instruments Widebus

Contextual Info: SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER www.ti.com SCES287D – OCTOBER 1999 – REVISED MAY 2005 FEATURES • • • • • • • • • • • • • • Member of the Texas Instruments Widebus Family UBT™ Transceiver Combines D-Type Latches

A115-A

Abstract: C101 SN74GTLP2034 Signal path designer
Contextual Info: SN74GTLP2034 8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001 D D D D D D D D D D D D D Member of the Texas Instruments Widebus Family TI-OPC Circuitry Limits Ringing on

74GTLPH16945GRE4

Abstract: SN74GTLPH16945 SN74GTLPH16945GR SN74GTLPH16945KR SN74GTLPH16945VR
Contextual Info: SN74GTLPH16945 16-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com FEATURES • • • • • • • • • • • • Member of the Texas Instruments Widebus Family TI-OPC™ Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC™ Circuitry Improves Signal Integrity and

A115-A

Abstract: C101 SN74GTLPH16916 SN74GTLPH16916GR
Contextual Info: www.ti.com SN74GTLPH16916 17-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS FEATURES • • • • • • • • • • • • • • • Member of the Texas Instruments Widebus Family UBT™ Transceiver Combines D-Type Latches

SN74GTLPH306

Contextual Info: SN74GTLPH306 8-BIT LVTTL-TO-GTL+ BUS TRANSCEIVER SCES284A – OCTOBER 1999 – REVISED DECEMBER 1999 D D D D D D D D DGV, DW, OR PW PACKAGE TOP VIEW Bidirectional Interface Between GTL+ Signal Levels and LVTTL Logic Levels Equivalent to ’245 Function LVTTL Interfaces Are 5-V Tolerant

SN74GTLPH16945

Contextual Info: SN74GTLPH16945 16-BIT LVTTL-TO-GTL+ BUS TRANSCEIVER SCES292 – OCTOBER 1999 D D D D D D D D D DGG, DGV, OR DL PACKAGE TOP VIEW Bidirectional Interface Between GTL+ Signal Levels and LVTTL Logic Levels LVTTL Interfaces Are 5-V Tolerant Identical to ’16245 Function

Contextual Info: SN74GTLPH32945 32-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES293C – OCTOBER 1999 – REVISED JUNE 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family TI-OPC™ Circuitry Limits Ringing on Unevenly Loaded Backplanes

Contextual Info: SN74GTLPH32945 32-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES293C – OCTOBER 1999 – REVISED JUNE 2005 FEATURES • • • • • • Member of the Texas Instruments Widebus+ Family TI-OPC™ Circuitry Limits Ringing on Unevenly Loaded Backplanes

Contextual Info: SN74GTLPH1655 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER www.ti.com FEATURES • • • • • • • • • • • • • • • Member of Texas Instruments' Widebus Family UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in

Contextual Info: SN74GTLPH32916 34-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS www.ti.com SCES380A – JANUARY 2002 – REVISED JUNE 2005 FEATURES • • • • • • • • Member of the Texas Instruments Widebus+ Family UBT™ Transceiver Combines D-Type Latches

Contextual Info: SN74GTLP2033 8ĆBIT LVTTLĆTOĆGTLP ADJUSTABLEĆEDGEĆRATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH SCES352C − JUNE 2001 − REVISED SEPTEMBER 2001 DGG OR DGV PACKAGE TOP VIEW D Member of the Texas Instruments D D D D D D D D D D