SIP475 Search Results

zo 402

Abstract: 125OC SIP4-105 SIP4-155 SIP4-205 SIP4-255 SIP4-55
Contextual Info: SIP4 Series 5-Tap High Performance Passive Delay Modules Operating Specifications - Passive Delay Lines Fast Rise Time, Low DCR High Bandwidth Pulse Overshoot Pos . 5% to 10%, typical Pulse Distortion (S) . 3% typical

P4-1007

Contextual Info: SIP4 Series High Performance Passive 5-Tap Delay Modules • Fast Rise Time, Low DCR • High Bandwidth ^ 0.35 / tr • Low Distortion LC N etwork • SIP4: 5 Equal D elay Taps 5-Tap SIP4 Style Schematic /T n p P pTh *—1 •T- • S tandard Impedances: 50 - 75 - 100 - 200 Q

Active (Logic Buffered)

Abstract: AML12-1 SP24L10005 SMD transistor M05 AMY-5 LVMDM-45G PLDM7-2.5 SMD 0505 RESISTOR 10K OHMS smd 2d 1002 -reel TZB4* "cross reference"
Contextual Info: Rhombus Industries Inc. 2001 Transformers & Magnetic Products Delay Lines Electromagnetic ∆t Logic Buffered Delay Low Distortion Buffered Input / Output Fast Rise Times 5V FAST/TTL & Advanced CMOS Single Output 5 Taps 10 Taps 16 Taps 20 Taps 3V Logic, Low Voltage CMOS

Contextual Info: • • SIP4 & SIP5 Series High Performance Passive Delay Modules Operating Specifications - Passive Delay Lines Fast Rise Time, Low D C R ~ High Bandwidth Pulse Overshoot P os . 5% to 10%, typical Pulse Distortion (S ). 3% typical

8205S

Contextual Info: SIP4 Series High Performance Passive 5-Tap Delay Modules • Fast Rise Time, Low DCR • High Bandwidth ~ 0.35 / 1 • Low Distortion LC Network • SIP4: 5 Equal Delay Taps 5-Tap SIP4 Style Schematic 'T- p T p T 7 ' r i 'T' 'T' COM IN h H • Standard Impedances: 50 - 75- 100 - 200 Q

SIP4

Abstract: SIP4_5 ZO 405 me SIP4-155 SIP4-205 SIP4-255 SIP4-305 SIP4-355 SIP4-405 SIP4-55
Contextual Info: SIP4 Series High Performance Passive 5-Tap Delay Modules Fast Rise Time, Low DCR High Bandwidth 0.35 / tr Low Distortion LC Network SIP4: 5 Equal Delay Taps 5-Tap SIP4 Style Schematic Standard Impedances: 50 - 75 - 100 - 200 Ω 1 2 3 COM IN 20% 4 40% 5 60%

Contextual Info: Electrical Specifications at 25°C - See General Specifications top of page 13 Delay Tolerances Total 50 Ohm Impedance Tap-to-Tap ns (ns) 5 ±0.50 1011.00 15 ±1.00 20 ±1.00 25 ±1.25 30 ±1.50 35 ±1.75 40 ±2.00 45 ±2.25 50 ±2.50 55 ±2.75 60 ±3.00

Delay Lines

Abstract: SMD 0505 RESISTOR 10K OHMS SMD transistor M05 equivalent ZO 607 TZB12-5 TF80 AMY-5 analog delay line schematic AML1-12-10 PLDM7-2.5
Contextual Info: Rhombus Industries Inc. 2002 Transformers & Magnetic Products Delay Lines Electromagnetic ∆t Logic Buffered Delay Low Distortion Buffered Input / Output Fast Rise Times 5V FAST/TTL & Advanced CMOS Single Output 5 Taps 10 Taps 16 Taps 20 Taps 3V Logic, Low Voltage CMOS

OCR 455

Contextual Info: High Performance 5-Tap Passive Delay SIP Modules Low Distortion LC Network Fast Rise Time, High Bandwidth Stable Delay vs. Temperature 5 Equal Delay Taps SI f»4 - XXX X Part Number Description Pulse Overshoot P o s .5% to 10%, typical