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    SIO TABLE Search Results

    SIO TABLE Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    PSAS4F2130132TR Amphenol Communications Solutions U.3 SAS PCIe 4.0, 68pin, Socket, Right Angle reverse, SIO pin Visit Amphenol Communications Solutions
    PSASF3130271TRW Amphenol Communications Solutions SAS PCIe,12G,Storage and server connector, 68pin, socket, Vertical, Surface Mount, high durability, with SIO pins Visit Amphenol Communications Solutions
    LM2512ASN/NOPB Texas Instruments Mobile Pixel Link (MPL-1) 24Bit RGB Display Interf Serializer w/ Optional Dithering & Look Up Table 40-X2QFN -30 to 85 Visit Texas Instruments Buy
    DAC539G2RTERQ1 Texas Instruments Automotive, 10-bit look-up-table based GPI-to-PWM converter for a single-wire error communication 16-WQFN -40 to 125 Visit Texas Instruments
    DAC539G2WRTERQ1 Texas Instruments Automotive, 10-bit look-up-table based GPI-to-PWM converter for a single-wire error communication 16-WQFN -40 to 125 Visit Texas Instruments

    SIO TABLE Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    marking WR6

    Abstract: 43AF-6 SIO129 TMPZ84C40 TMPZ84C43AF-6 42AP-8 IN SDLC PROTOCOL ssop40 TMPZ84C40AM-6 TMPZ84C44AT-6
    Text: TOSHIBA TMPZ84C40A/41A/42A/43A/44A TMPZ84C40AP-6 / 41AP-6 / 42AP-6 / 43AF-6 / 44AT-6 TMPZ84C40AM-6 / 41 AM-6 / 42AM-6 TMPZ84C40AP-8 / 41AP-8 / 42AP-8 TLCS-Z80 SIO: SERIAL INPUT/OUTPUT CONTROLLER 1. GENERAL DESCRIPTION AND FEATURES The TMPZ84C40A SIO/O , TMPZ84C41A (SIO/1), TMPZ84C42A (SIO/2),


    OCR Scan     		TMPZ84C40A/41A/42A/43 TMPZ84C40AP-6 41AP-6 42AP-6 43AF-6 44AT-6 TMPZ84C40AM-6 41AM-6 42AM-6 TMPZ84C40AP-8 marking WR6 SIO129 TMPZ84C40 TMPZ84C43AF-6 42AP-8 IN SDLC PROTOCOL ssop40 TMPZ84C44AT-6 PDF

    TMPZ84

    Abstract: TMPZ84C40
    Text: TO SH IBA TMPZ84C40A/41A/42A/43A/44A TMPZ84C40AP-6 / 41AP-6 / 42AP-6 / 43AF-6 / 44AT-6 TMPZ84C40AM-6 /41AM-6 / 42AM-6 TMPZ84C40AP-8 / 41AP-8 / 42AP-8 TLCS-Z80 SIO: SERIAL INPUT/OUTPUT CONTROLLER 1. GENERAL DESCRIPTION AND FEATURES The TMPZ84C40A SIO/O , TMPZ84C41A (SIO/1), TMPZ84C42A (SIO/2),


    OCR Scan     		TMPZ84C40A/41A/42A/43A/44A TMPZ84C40AP-6 41AP-6 42AP-6 43AF-6 44AT-6 TMPZ84C40AM-6 /41AM-6 42AM-6 TMPZ84C40AP-8 TMPZ84 TMPZ84C40 PDF

    marking WR6

    Abstract: No abstract text available
    Text: T O S H IB A T M PZ84C40 A/41 A/42 A/43A/44A TMPZ84C40AP-6 / 41AP-6 / 42AP-6 / 43AF-6 / 44AT-6 TMPZ84C40AM-6 / 41 AM-6 / 42AM-6 TMPZ84C40AP-8 / 41AP-8 / 42AP-8 TLCS-Z80 SIO: SERIAL INPUT/OUTPUT CONTROLLER 1. GENERAL DESCRIPTION AND FEATURES The TMPZ84C40A SIO/O , TMPZ84C41A (SIO/1), TMPZ84C42A (SIO/2),


    OCR Scan     		PZ84C40 /43A/44A TMPZ84C40AP-6 41AP-6 42AP-6 43AF-6 44AT-6 TMPZ84C40AM-6 42AM-6 TMPZ84C40AP-8 marking WR6 PDF

    LPT port male D-type

    Abstract: JP24 mouse driver CONNECTOR 8 PIN Round rs485 25-WAY computer mouse circuit diagram
    Text: SIO-4d Multi-Channel Serial Communications Board User Manual SIO-4d User Manual Document Part N° Document Reference Document Issue Level 127-169 SIO-4d\.\127-169.DOC 1.2 Manual covers PCBs identified KFS-10 Rev. C All rights reserved. No part of this publication may be reproduced, stored in any retrieval system, or


    Original     		KFS-10 LPT port male D-type JP24 mouse driver CONNECTOR 8 PIN Round rs485 25-WAY computer mouse circuit diagram PDF

    rx 05f

    Abstract: LPT port male D-type rs485 serial card datasheet JP24 D type 25 Way plug 25 Way D-Type Socket
    Text: SIO-4d Multi-Channel Serial Communications Board User Manual SIO-4d User Manual Document Part N° Document Reference Document Issue Level 0127-0169 SIO-4d\.\0127-0169.doc 1.2 Manual covers PCBs identified KFS-10 Rev. C All rights reserved. No part of this publication may be reproduced, stored in any retrieval system, or


    Original     		KFS-10 rx 05f LPT port male D-type rs485 serial card datasheet JP24 D type 25 Way plug 25 Way D-Type Socket PDF

    Untitled

    Abstract: No abstract text available
    Text: THIS SPEC IS OBSOLETE Spec No: 001-07162 Spec Title: CY7C1393CV18, CY7C1394CV18 18-MBIT DDR II SIO SRAM 2-WORD BURST ARCHITECTURE Sunset Owner: Jayasree Nayar NJY Replaced by: NONE CY7C1393CV18 CY7C1394CV18 18-Mbit DDR II SIO SRAM 2-Word Burst Architecture


    Original     		CY7C1393CV18, CY7C1394CV18 18-MBIT CY7C1393CV18 CY7C1394CV18 PDF

    Untitled

    Abstract: No abstract text available
    Text: K7J643682M K7J641882M Preliminary 2Mx36 & 4Mx18 DDR II SIO b2 SRAM Document Title 2Mx36-bit, 4Mx18-bit DDR II SIO b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Mar. 9, 2003 Advance 0.1 1. Correct the JTAG ID register definition


    Original     		K7J643682M K7J641882M 2Mx36 4Mx18 2Mx36-bit, 4Mx18-bit PDF

    AN5062

    Abstract: No abstract text available
    Text: THIS SPEC IS OBSOLETE Spec No: 001-44698 Spec Title: CY7C1393JV18 CY7C1394JV18, 18 MBIT DDR II SIO SRAM TWO WORD BURST ARCHITECTURE Sunset Owner: N Vijay Kumar VKN Replaced by: None CY7C1393JV18 CY7C1394JV18 18 Mbit DDR II SIO SRAM Two Word Burst Architecture


    Original     		CY7C1393JV18 CY7C1394JV18, CY7C1394JV18 CY7C1393JV18, CY7C1394JV18 AN5062 PDF

    Untitled

    Abstract: No abstract text available
    Text: THIS SPEC IS OBSOLETE Spec No: 001-06981 Spec Title: CY7C1523AV18/CY7C1524AV18, 72-MBIT DDR II SIO SRAM 2-WORD BURST ARCHITECTURE Sunset Owner: Jayasree Nayar NJY Replaced by: None CY7C1523AV18 CY7C1524AV18 72-Mbit DDR II SIO SRAM 2-Word Burst Architecture


    Original     		CY7C1523AV18/CY7C1524AV18, 72-MBIT CY7C1523AV18 CY7C1524AV18 CY7C1524AV18 PDF

    Untitled

    Abstract: No abstract text available
    Text: K7J643682M K7J641882M Preliminary 2Mx36 & 4Mx18 DDR II SIO b2 SRAM Document Title 2Mx36-bit, 4Mx18-bit DDR II SIO b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Mar. 9, 2003 Advance 0.1 1. Correct the JTAG ID register definition


    Original     		K7J643682M K7J641882M 2Mx36 4Mx18 2Mx36-bit, 4Mx18-bit PDF

    K7J321882M

    Abstract: K7J321882M-FC16 K7J321882M-FC20 K7J321882M-FC25 K7J323682M K7J323682M-FC16 K7J323682M-FC20 K7J323682M-FC25
    Text: K7J323682M K7J321882M K7J320882M Preliminary 1Mx36 & 2Mx18 & 4Mx8 DDR II SIO b2 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx8-bit DDR II SIO b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. July, 15 200 1 Advance 0.1 1. 2. 3. 4.


    Original     		K7J323682M K7J321882M K7J320882M 1Mx36 2Mx18 1Mx36-bit, 2Mx18-bit, K7J321882M K7J321882M-FC16 K7J321882M-FC20 K7J321882M-FC25 K7J323682M K7J323682M-FC16 K7J323682M-FC20 K7J323682M-FC25 PDF

    K7J161882B

    Abstract: K7J161882B-FC20 K7J161882B-FC25 K7J161882B-FC30 K7J163682B K7J163682B-FC16 K7J163682B-FC20 K7J163682B-FC25 K7J163682B-FC30
    Text: K7J163682B K7J161882B 512Kx36 & 1Mx18 DDR II SIO b2 SRAM Document Title 512Kx36-bit, 1Mx18-bit DDR II SIO b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Dec. 16, 2002 Advance 0.1 1. Change the JTAG Block diagram Dec. 26, 2002 Preliminary


    Original     		K7J163682B K7J161882B 512Kx36 1Mx18 512Kx36-bit, 1Mx18-bit 165FBGA K7J161882B K7J161882B-FC20 K7J161882B-FC25 K7J161882B-FC30 K7J163682B K7J163682B-FC16 K7J163682B-FC20 K7J163682B-FC25 K7J163682B-FC30 PDF

    D0-35

    Abstract: K7J161882B K7J161882B-FC16 K7J161882B-FC20 K7J161882B-FC25 K7J163682B K7J163682B-FC16 K7J163682B-FC20 K7J163682B-FC25
    Text: K7J163682B K7J161882B 512Kx36 & 1Mx18 DDR II SIO b2 SRAM Document Title 512Kx36-bit, 1Mx18-bit DDR II SIO b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Dec. 16, 2002 Advance 0.1 1. Change the JTAG Block diagram Dec. 26, 2002 Preliminary


    Original     		K7J163682B K7J161882B 512Kx36 1Mx18 512Kx36-bit, 1Mx18-bit 165FBGA D0-35 K7J161882B K7J161882B-FC16 K7J161882B-FC20 K7J161882B-FC25 K7J163682B K7J163682B-FC16 K7J163682B-FC20 K7J163682B-FC25 PDF

    Untitled

    Abstract: No abstract text available
    Text: K7J323682M K7J321882M K7J320882M Preliminary 1Mx36 & 2Mx18 & 4Mx8 DDR II SIO b2 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx8-bit DDR II SIO b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. July, 15 200 1 Advance 0.1 1. 2. 3. 4.


    Original     		K7J323682M K7J321882M K7J320882M 1Mx36 2Mx18 1Mx36-bit, 2Mx18-bit, PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1523KV18 72-Mbit DDR II SIO SRAM Two-Word Burst Architecture 72-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features Configurations • 72-Mbit density 4 M x 18 CY7C1523KV18 – 4 M × 18 ■ 250 MHz clock for high bandwidth Functional Description


    Original     		CY7C1523KV18 72-Mbit PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1623KV18 144-Mbit DDR-II SIO SRAM Two-Word Burst Architecture 144-Mbit DDR-II SIO SRAM Two-Word Burst Architecture Features Configuration • 144-Mbit density 8 M x 18 CY7C1623KV18 – 8 M × 18 ■ 333 MHz clock for high bandwidth Functional Description


    Original     		CY7C1623KV18 144-Mbit PDF

    AC power SAVING CIRCUIT DIAGRAM

    Abstract: CY7C1623KV18 3M Touch Systems
    Text: CY7C1623KV18 144-Mbit DDR-II SIO SRAM 2-Word Burst Architecture 144-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features Configuration • 144-Mbit density 8 M x 18 CY7C1623KV18 – 8 M × 18 ■ 333 MHz clock for high bandwidth Functional Description


    Original     		CY7C1623KV18 144-Mbit AC power SAVING CIRCUIT DIAGRAM CY7C1623KV18 3M Touch Systems PDF

    K7J641882M

    Abstract: K7J641882M-FC25 K7J641882M-FC30 K7J643682M K7J643682M-FC16 K7J643682M-FC20 K7J643682M-FC25 K7J643682M-FC30
    Text: K7J643682M K7J641882M K7J640882M Preliminary 2Mx36 & 4Mx18 & 8Mx8 DDR II SIO b2 SRAM Document Title 2Mx36-bit, 4Mx18-bit, 8Mx8-bit DDR II SIO b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Mar. 9, 2003 Advance 0.1 1. Correct the JTAG ID register definition


    Original     		K7J643682M K7J641882M K7J640882M 2Mx36 4Mx18 2Mx36-bit, 4Mx18-bit, K7J641882M K7J641882M-FC25 K7J641882M-FC30 K7J643682M K7J643682M-FC16 K7J643682M-FC20 K7J643682M-FC25 K7J643682M-FC30 PDF

    CY7C1523KV18

    Abstract: 3M Touch Systems
    Text: CY7C1523KV18 72-Mbit DDR II SIO SRAM 2-Word Burst Architecture 72-Mbit DDR II SIO SRAM 2-Word Burst Architecture Features Configurations • 72-Mbit density 4 M x 18 CY7C1523KV18 – 4 M × 18 ■ 250 MHz clock for high bandwidth Functional Description


    Original     		CY7C1523KV18 72-Mbit CY7C1523KV18 3M Touch Systems PDF

    K7J161882B

    Abstract: K7J161882B-FC25 K7J161882B-FC30 K7J163682B K7J163682B-FC16 K7J163682B-FC20 K7J163682B-FC25 K7J163682B-FC30 SRAM sheet samsung
    Text: K7J163682B K7J161882B K7J160882B Preliminary 512Kx36 & 1Mx18 & 2Mx8 DDR II SIO b2 SRAM Document Title 512Kx36-bit, 1Mx18-bit, 2Mx8-bit DDR II SIO b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Dec. 16, 2002 Advance 0.1 1. Change the JTAG Block diagram


    Original     		K7J163682B K7J161882B K7J160882B 512Kx36 1Mx18 512Kx36-bit, 1Mx18-bit, 165FBGA K7J161882B K7J161882B-FC25 K7J161882B-FC30 K7J163682B K7J163682B-FC16 K7J163682B-FC20 K7J163682B-FC25 K7J163682B-FC30 SRAM sheet samsung PDF

    3M Touch Systems

    Abstract: No abstract text available
    Text: CY7C1623KV18 144-Mbit DDR-II SIO SRAM Two-Word Burst Architecture 144-Mbit DDR-II SIO SRAM Two-Word Burst Architecture Features Configuration • 144-Mbit density 8 M x 18 CY7C1623KV18 – 8 M × 18 ■ 333 MHz clock for high bandwidth Functional Description


    Original     		CY7C1623KV18 144-Mbit 3M Touch Systems PDF

    74AC165

    Abstract: iF80H-1FBFH 80C196NP IF80H 8XC196MH SF 119 D AD7893 p210w0 LD 7576 OS 8067H
    Text: Using the SIO on the 8xC196MH Application Brief AB-71 December 2000 Order Number: 272594-002 Using the SIO on the 8xC196MH Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual


    Original     		8xC196MH AB-71) 74AC165 iF80H-1FBFH 80C196NP IF80H 8XC196MH SF 119 D AD7893 p210w0 LD 7576 OS 8067H PDF

    Untitled

    Abstract: No abstract text available
    Text: K7J163682B K7J161882B K7J160882B Preliminary 512Kx36 & 1Mx18 & 2Mx8 DDR II SIO b2 SRAM Document Title 512Kx36-bit, 1Mx18-bit, 2Mx8-bit DDR II SIO b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Dec. 16, 2002 Advance 0.1 1. Change the JTAG Block diagram


    Original     		K7J163682B K7J161882B K7J160882B 512Kx36 1Mx18 512Kx36-bit, 1Mx18-bit, 165FBGA PDF

    Untitled

    Abstract: No abstract text available
    Text: K7J163682B K7J161882B K7J160882B Preliminary 512Kx36 & 1Mx18 & 2Mx8 DDR II SIO b2 SRAM Document Title 512Kx36-bit, 1Mx18-bit, 2Mx8-bit DDR II SIO b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Dec. 16, 2002 Advance 0.1 1. Change the JTAG Block diagram


    Original     		K7J163682B K7J161882B K7J160882B 512Kx36 1Mx18 512Kx36-bit, 1Mx18-bit, K7J163682BtCHDX PDF