marking WR6
Abstract: 43AF-6 SIO129 TMPZ84C40 TMPZ84C43AF-6 42AP-8 IN SDLC PROTOCOL ssop40 TMPZ84C40AM-6 TMPZ84C44AT-6
Text: TOSHIBA TMPZ84C40A/41A/42A/43A/44A TMPZ84C40AP-6 / 41AP-6 / 42AP-6 / 43AF-6 / 44AT-6 TMPZ84C40AM-6 / 41 AM-6 / 42AM-6 TMPZ84C40AP-8 / 41AP-8 / 42AP-8 TLCS-Z80 SIO: SERIAL INPUT/OUTPUT CONTROLLER 1. GENERAL DESCRIPTION AND FEATURES The TMPZ84C40A SIO/O , TMPZ84C41A (SIO/1), TMPZ84C42A (SIO/2),
|
OCR Scan
|
TMPZ84C40A/41A/42A/43
TMPZ84C40AP-6
41AP-6
42AP-6
43AF-6
44AT-6
TMPZ84C40AM-6
41AM-6
42AM-6
TMPZ84C40AP-8
marking WR6
SIO129
TMPZ84C40
TMPZ84C43AF-6
42AP-8
IN SDLC PROTOCOL
ssop40
TMPZ84C44AT-6
|
PDF
|
TMPZ84
Abstract: TMPZ84C40
Text: TO SH IBA TMPZ84C40A/41A/42A/43A/44A TMPZ84C40AP-6 / 41AP-6 / 42AP-6 / 43AF-6 / 44AT-6 TMPZ84C40AM-6 /41AM-6 / 42AM-6 TMPZ84C40AP-8 / 41AP-8 / 42AP-8 TLCS-Z80 SIO: SERIAL INPUT/OUTPUT CONTROLLER 1. GENERAL DESCRIPTION AND FEATURES The TMPZ84C40A SIO/O , TMPZ84C41A (SIO/1), TMPZ84C42A (SIO/2),
|
OCR Scan
|
TMPZ84C40A/41A/42A/43A/44A
TMPZ84C40AP-6
41AP-6
42AP-6
43AF-6
44AT-6
TMPZ84C40AM-6
/41AM-6
42AM-6
TMPZ84C40AP-8
TMPZ84
TMPZ84C40
|
PDF
|
marking WR6
Abstract: No abstract text available
Text: T O S H IB A T M PZ84C40 A/41 A/42 A/43A/44A TMPZ84C40AP-6 / 41AP-6 / 42AP-6 / 43AF-6 / 44AT-6 TMPZ84C40AM-6 / 41 AM-6 / 42AM-6 TMPZ84C40AP-8 / 41AP-8 / 42AP-8 TLCS-Z80 SIO: SERIAL INPUT/OUTPUT CONTROLLER 1. GENERAL DESCRIPTION AND FEATURES The TMPZ84C40A SIO/O , TMPZ84C41A (SIO/1), TMPZ84C42A (SIO/2),
|
OCR Scan
|
PZ84C40
/43A/44A
TMPZ84C40AP-6
41AP-6
42AP-6
43AF-6
44AT-6
TMPZ84C40AM-6
42AM-6
TMPZ84C40AP-8
marking WR6
|
PDF
|
NS16450N
Abstract: intel 8250 amstrad RS232 mouse diagram serial adapter cards for IBM PC asyst rs232 R232 notebook led display pinout WS4000
Text: SIO-2 2 Channel Serial Communications Board User Manual SIO-2 User Manual Document Part N° Document Reference Document Issue Level 0127-0001 0127-0001.Doc 0.6 Manual covers PCBs identified SIO-2 Rev. C All rights reserved. No part of this publication may be reproduced, stored in any retrieval system, or
|
Original
|
|
PDF
|
z80 qfp 80 pin
Abstract: 84 pin cpu Z80CPU
Text: B lo ck 84COO CPU D iagram SIO Power Down CTC CTC CGC P10 PIO SIO WDT SIO CSC WDT PIA Z80CPU CTC Z80CPU P art Num ber Z84C01 ZS4C90 Z84013/Z84C13 D escriptio n Z80 CPU with Clock Generalor/Clock Killer I/O Three Z80® Peripherals Intelligent Peripheral Controller
|
OCR Scan
|
84COO
Z80CPU
Z84C01
ZS4C90
Z84013/Z84C13
Z84013
Z84C13
Z84015/Z84C15
Z84015
z80 qfp 80 pin
84 pin cpu
Z80CPU
|
PDF
|
LPT port male D-type
Abstract: JP24 mouse driver CONNECTOR 8 PIN Round rs485 25-WAY computer mouse circuit diagram
Text: SIO-4d Multi-Channel Serial Communications Board User Manual SIO-4d User Manual Document Part N° Document Reference Document Issue Level 127-169 SIO-4d\.\127-169.DOC 1.2 Manual covers PCBs identified KFS-10 Rev. C All rights reserved. No part of this publication may be reproduced, stored in any retrieval system, or
|
Original
|
KFS-10
LPT port male D-type
JP24
mouse driver
CONNECTOR 8 PIN Round rs485
25-WAY
computer mouse circuit diagram
|
PDF
|
Untitled
Abstract: No abstract text available
Text: K7J643682M K7J641882M Preliminary 2Mx36 & 4Mx18 DDR II SIO b2 SRAM Document Title 2Mx36-bit, 4Mx18-bit DDR II SIO b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Mar. 9, 2003 Advance 0.1 1. Correct the JTAG ID register definition
|
Original
|
K7J643682M
K7J641882M
2Mx36
4Mx18
2Mx36-bit,
4Mx18-bit
|
PDF
|
Untitled
Abstract: No abstract text available
Text: THIS SPEC IS OBSOLETE Spec No: 001-06981 Spec Title: CY7C1523AV18/CY7C1524AV18, 72-MBIT DDR II SIO SRAM 2-WORD BURST ARCHITECTURE Sunset Owner: Jayasree Nayar NJY Replaced by: None CY7C1523AV18 CY7C1524AV18 72-Mbit DDR II SIO SRAM 2-Word Burst Architecture
|
Original
|
CY7C1523AV18/CY7C1524AV18,
72-MBIT
CY7C1523AV18
CY7C1524AV18
CY7C1524AV18
|
PDF
|
Untitled
Abstract: No abstract text available
Text: K7J643682M K7J641882M Preliminary 2Mx36 & 4Mx18 DDR II SIO b2 SRAM Document Title 2Mx36-bit, 4Mx18-bit DDR II SIO b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Mar. 9, 2003 Advance 0.1 1. Correct the JTAG ID register definition
|
Original
|
K7J643682M
K7J641882M
2Mx36
4Mx18
2Mx36-bit,
4Mx18-bit
|
PDF
|
K7J321882M
Abstract: K7J321882M-FC16 K7J321882M-FC20 K7J321882M-FC25 K7J323682M K7J323682M-FC16 K7J323682M-FC20 K7J323682M-FC25
Text: K7J323682M K7J321882M K7J320882M Preliminary 1Mx36 & 2Mx18 & 4Mx8 DDR II SIO b2 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx8-bit DDR II SIO b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. July, 15 200 1 Advance 0.1 1. 2. 3. 4.
|
Original
|
K7J323682M
K7J321882M
K7J320882M
1Mx36
2Mx18
1Mx36-bit,
2Mx18-bit,
K7J321882M
K7J321882M-FC16
K7J321882M-FC20
K7J321882M-FC25
K7J323682M
K7J323682M-FC16
K7J323682M-FC20
K7J323682M-FC25
|
PDF
|
16c550
Abstract: rs485 RS485 rs232 UART windows
Text: ACQUISITION CARDS SIO-2 DATA 2 Channel Serial Communications Card The SIO-2 card allows serial communications between computers, printers, plotters, screen, PID controllers, instruments and any other device with a serial interface. 2 serial channels Link selectable RS232, RS422, RS485 or 20mA loop
|
Original
|
RS232,
RS422,
RS485
16C550
RS232
RS485,
150mA
107mm
RS485 rs232
UART windows
|
PDF
|
D0-35
Abstract: K7J161882B K7J161882B-FC16 K7J161882B-FC20 K7J161882B-FC25 K7J163682B K7J163682B-FC16 K7J163682B-FC20 K7J163682B-FC25
Text: K7J163682B K7J161882B 512Kx36 & 1Mx18 DDR II SIO b2 SRAM Document Title 512Kx36-bit, 1Mx18-bit DDR II SIO b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Dec. 16, 2002 Advance 0.1 1. Change the JTAG Block diagram Dec. 26, 2002 Preliminary
|
Original
|
K7J163682B
K7J161882B
512Kx36
1Mx18
512Kx36-bit,
1Mx18-bit
165FBGA
D0-35
K7J161882B
K7J161882B-FC16
K7J161882B-FC20
K7J161882B-FC25
K7J163682B
K7J163682B-FC16
K7J163682B-FC20
K7J163682B-FC25
|
PDF
|
Untitled
Abstract: No abstract text available
Text: CY7C1523KV18 72-Mbit DDR II SIO SRAM Two-Word Burst Architecture 72-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features Configurations • 72-Mbit density 4 M x 18 CY7C1523KV18 – 4 M × 18 ■ 250 MHz clock for high bandwidth Functional Description
|
Original
|
CY7C1523KV18
72-Mbit
|
PDF
|
Untitled
Abstract: No abstract text available
Text: CY7C1623KV18 144-Mbit DDR-II SIO SRAM Two-Word Burst Architecture 144-Mbit DDR-II SIO SRAM Two-Word Burst Architecture Features Configuration • 144-Mbit density 8 M x 18 CY7C1623KV18 – 8 M × 18 ■ 333 MHz clock for high bandwidth Functional Description
|
Original
|
CY7C1623KV18
144-Mbit
|
PDF
|
|
|
K7J641882M
Abstract: K7J641882M-FC25 K7J641882M-FC30 K7J643682M K7J643682M-FC16 K7J643682M-FC20 K7J643682M-FC25 K7J643682M-FC30
Text: K7J643682M K7J641882M K7J640882M Preliminary 2Mx36 & 4Mx18 & 8Mx8 DDR II SIO b2 SRAM Document Title 2Mx36-bit, 4Mx18-bit, 8Mx8-bit DDR II SIO b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Mar. 9, 2003 Advance 0.1 1. Correct the JTAG ID register definition
|
Original
|
K7J643682M
K7J641882M
K7J640882M
2Mx36
4Mx18
2Mx36-bit,
4Mx18-bit,
K7J641882M
K7J641882M-FC25
K7J641882M-FC30
K7J643682M
K7J643682M-FC16
K7J643682M-FC20
K7J643682M-FC25
K7J643682M-FC30
|
PDF
|
CY7C1523KV18
Abstract: 3M Touch Systems
Text: CY7C1523KV18 72-Mbit DDR II SIO SRAM 2-Word Burst Architecture 72-Mbit DDR II SIO SRAM 2-Word Burst Architecture Features Configurations • 72-Mbit density 4 M x 18 CY7C1523KV18 – 4 M × 18 ■ 250 MHz clock for high bandwidth Functional Description
|
Original
|
CY7C1523KV18
72-Mbit
CY7C1523KV18
3M Touch Systems
|
PDF
|
microcontroller 8501
Abstract: S1C33000 S1C33209
Text: S1C33209 32-bit Single Chip Microcontroller ● ● ● ● ● ● High-speed 32-bit RISC Core Multiply Accumulation Built-in 8K-byte RAM 10-bit ADC 4-ch. SIO High-speed DMA, Intelligent DMA DESCRIPTIONS The S1C33209 is a CMOS 32-bit microcomputer composed of a CMOS 32-bit RISC core, 8K-byte RAM, 4-channel SIO, A/D
|
Original
|
S1C33209
32-bit
10-bit
S1C33209
microcontroller 8501
S1C33000
|
PDF
|
Untitled
Abstract: No abstract text available
Text: K7J163682B K7J161882B K7J160882B Preliminary 512Kx36 & 1Mx18 & 2Mx8 DDR II SIO b2 SRAM Document Title 512Kx36-bit, 1Mx18-bit, 2Mx8-bit DDR II SIO b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Dec. 16, 2002 Advance 0.1 1. Change the JTAG Block diagram
|
Original
|
K7J163682B
K7J161882B
K7J160882B
512Kx36
1Mx18
512Kx36-bit,
1Mx18-bit,
165FBGA
|
PDF
|
Untitled
Abstract: No abstract text available
Text: K7J163682B K7J161882B K7J160882B Preliminary 512Kx36 & 1Mx18 & 2Mx8 DDR II SIO b2 SRAM Document Title 512Kx36-bit, 1Mx18-bit, 2Mx8-bit DDR II SIO b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Dec. 16, 2002 Advance 0.1 1. Change the JTAG Block diagram
|
Original
|
K7J163682B
K7J161882B
K7J160882B
512Kx36
1Mx18
512Kx36-bit,
1Mx18-bit,
K7J163682BtCHDX
|
PDF
|
Untitled
Abstract: No abstract text available
Text: CY7C1392KV18 CY7C1393KV18 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features Configurations • 18-Mbit density 2 M x 8, 1 M × 18 CY7C1392KV18 – 2 M × 8 ■ 333-MHz clock for high bandwidth
|
Original
|
CY7C1392KV18
CY7C1393KV18
18-Mbit
333-MHz
|
PDF
|
Untitled
Abstract: No abstract text available
Text: CY7C1423KV18/CY7C1424KV18 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features Configurations • 36-Mbit density 2 M x 18, 1 M × 36 CY7C1423KV18 – 2 M × 18 ■ 333 MHz clock for high bandwidth
|
Original
|
CY7C1423KV18/CY7C1424KV18
36-Mbit
CY7C1423KV18
CY7C1424KV18
|
PDF
|
ibm rs485
Abstract: No abstract text available
Text: ACQUISITION CARDS SIO-4D DATA 4 Channel Serial Communication Card The SIO-4d provides the user with four serial communications channels and two parallel printer ports. Each serial channel may be configured to appear as “COM 1” to “COM 8” within the PC port map. Each
|
Original
|
RS-232
RS-485
RS-485
ibm rs485
|
PDF
|
MT49H16M18C
Abstract: No abstract text available
Text: 16 Meg x 18 2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II Features 288Mb SIO Reduced Latency RLDRAM II MT49H16M18C For the latest data sheet, refer to Micron’s Web site: www.micron.com/rldram Features Figure 1: • 400 MHz DDR operation (800 Mb/s/pin data rate)
|
Original
|
288Mb
MT49H16M18C
09005aef80a41b59/Source:
09005aef811ba111
MT49H8M18C
MT49H16M18C
|
PDF
|
15READ
Abstract: marking ba5 MT49H8M18C MT49H16M18C
Text: 288Mb: 16 Meg x 18 2.5V VEXT, 1.8V VDD, HSTL, SIO, RLDRAM II Features 288Mb SIO Reduced Latency RLDRAM II MT49H16M18C For the latest data sheet, refer to Micron’s Web site: www.micron.com/rldram Features Figure 1: • 400 MHz DDR operation (800 Mb/s/pin data rate)
|
Original
|
288Mb:
288Mb
MT49H16M18C
09005aef80a41b59/Source:
09005aef811ba111
MT49H8M18C
15READ
marking ba5
MT49H16M18C
|
PDF
|
