SHARP MASK ROM Search Results

sharp mask rom

Abstract: LH53820 LH5322 lh5384
Contextual Info: SHARP CORP bGE D • 000^435 40 e! f l l f l ü ? » S R P J T - H é - o - jS SHARP LH5316400D ■ M Description The LH5316400D is a 16M bit CMOS mask ROM organized as 2,0 97 ,1 5 2 x8 bits. It is packaged in 36-pin DIP which provides mask ROM specific pinout compatible with 28-pin 1 M mask ROM.

lh5s4axx

Abstract: sharp mask rom LH53F4600 lh5s4 LH5S flash memory 4m 44-pin
Contextual Info: LH53F4600 4M Mask ROM SHARP LH53F4600 • Description Flash Memory Compatible pinout 4M-bit Mask-Programmable ROM ■ Pin Connections The LH53F4600N User’s No. : LH-5S4ZXX is a CMOS 4Mbit mask-programmable ROM organized as 524 288 X 8 bits (Byte mode) or 262 144 X 16 bits (Word mode) that can be

LH5324000D

Abstract: LH5324C00 LH5324C00D LH5365 sharp mask rom 48TSOP LH536
Contextual Info: SHARP NEW PRODUCT INFORMATION LH5324C00 • 24M-bit Mask-Programmable ROM ■ Description Pin Connections The LH5324C00D User’s No. : LH536CXX is a CMOS 24M-bit mask-programmable ROM organized as 1 572 864 X 16 bits. It is fabricated using sillicon-gate CMOS process

lh5348

Abstract: lh5s4 lh5348xx sharp mask rom LH534A00T LH5s LH534B00T 40-DIP
Contextual Info: NEW PRODUCT INFORMATION SHARP LH53H4100 • High-speed 4M-bit Mask-Programmable ROM ■ Description Pin Connections The LH53H4100D/N User's No. ! LH5H41XX is a CMOS 4M-bit mask-programmable ROM organized as 524 288 X 8 bits. It is fabricated using sillicon-gate CMOS process technology.

lh5s4

Abstract: lh5348 LH5s lh5s47xx 48-TSOP LH53H4100D LH53H4100N lh534y00d 48TSOP sharp mask rom
Contextual Info: NEW PRODUCT INFORMATION SHARP LH53 H4100 • Description High-speed 4M-bit Mask-Programmable ROM ■ Pin Connections The LH53H4100D/N User's No. ! LH5H41XX is a CMOS 4M-bit mask-programmable ROM organized as 524 288 X 8 bits. It is fabricated using sillicon-gate CMOS process technology.

lh5348

Abstract: lh5348xx sharp mask rom lh5s4
Contextual Info: NEW PRODUCT INFORMATION SHARP LH53 H 4100 • High-speed 4M-bit Mask-Programmable ROM ■ Description Pin Connections The LH53H4100D/N User’s No. : LH5H41XX is a CMOS 4M-bit mask-programmable ROM organized as 524 288 X 8 bits. It is fabricated using sillicon-gate CMOS process technology.

sharp mask rom

Contextual Info: SHARP CORP blE D • fllflcmfl flS2 H S R P J PRELIMINARY CMOS 4M 512K x 8 / 256K x 16 High-Speed Mask-Programmable ROM LH53H4000/ LH53H4100 CMOS 4M (512K x 8) High-Speed Mask-Programmable ROM FEATURES • • LH53H4000 524.288 x 8 / 262,144 x 16 bit organization

Contextual Info: MEMORIES Dynamic RAMs ! Sharp is able to meet the diverse demands of its customers by offering a comprehensive range of memory devices, including flash memories, which has started spreading in many fields including multimedia products. Mask ROMs, which offer

LH5364600

Contextual Info: LH5364600N 64M Mask ROM Model No.: LHMN06xx Spec No.: MR97Y04 Issue Date: November 27, 1997 SHARP LH5364600N •Handle this document carefully for it contains nterial protected by international copyright la*. Any reproduction, full or in part, of this raterial is prohibited

Contextual Info: LH53CV32800T 32M Mask ROM Model No.: LHME53xx Spec No.: EL097130 Issue Date: July 28, 1998 SHARP LH53CV32800T •Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited

LH5364600

Contextual Info: 64M Mask ROM Model No.: LHMNOBxx Spec No.: MR97Y05 Issue Date: November 27, 1997 SHARP LH5364600T •Handle this docuaent carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this «atería! is prohibited

Contextual Info: LH53C32600N 32M Mask ROM Model No.: LHMC56xx Spec No.: EL097186 Issue Date: August 5, 1997 SHARP LH53C32600N # Handle this docuaent carefully for it contains aaterial protected by international copyright law. Any reproduction, full or in part, of this laterial is prohibited

Contextual Info: LH53BV8600N 8M Mask ROM Model No.: LH5D86xx Spec No.: EL093164 Issue Date: May 8, 1998 SHARP LH53BV8600N •Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited

Contextual Info: LH53BV64900T 65M Mask ROM Model No.: LHMD09XX Spec No.: EL104059 Issue Date: May 12, 1998 SHARP LH53BV64900T •Handle this docuaent carefully for it contains aaterial protected by international copyright law. Any reproduction, full or in part, of this aaterial is prohibited

Contextual Info: Memories Sharp is able to meet the diverse demands of its customers by offering a comprehensive range of memory devices, including mask ROMs, which offer large capacity, high speed and a short turnaround time made possible by its proprietary technology. Static RAMs, for example, are

Contextual Info: Memories Sharp is able to meet the diverse demands of its customers by offering a comprehensive range of memory devices, including mask ROMs, which offer large capacity, high speed and a short turnaround time made possible by its proprietary technology. Static RAMs, for example, are

Contextual Info: L H 5 3 B 8 V 8M Mask ROM Model No.: LHMB8Vxx Spec No.: EL099187 Issue Date: November 6, 1997 D SHARP LH53B8V00D •Handle this docuaent carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited

sharp mask rom

Abstract: cd rom 40 pinout lh5348 lh5s4 LH5S
Contextual Info: NEW PRODUCT INFORMATION SHARP LH53H4000 • Description The LH53H4000D/N User's No. : LH5H40XX is a CMOS 4M-bit mask-programmable ROM organized as 524 288 X 8 bits (Byte mode) or 262 144 X 16 bits (Word mode) that can be selected by BYTE input pin. ■ Features

Sharp LJ

Contextual Info: SHARP I SPEC 1*0. 1 MR 9 6 3 0 7 ISSUE: Mar. 29 1996 To i SPECIFICAT IONS Product Type 8M bit MASK ROM LH5G8Pxx LH53FV8P00T-X SRTbis specifications contains 9 pages including the cover. If lou hare any objections, please contact us before issuing purchasing order.

VRAM

Contextual Info: SHARP SM8521 PIN DESCRIPTION PIN NAME I/O FUNCTION D0-D7 I/O External data bus External address bus Chip enable 0 Mask ROM/flash memory Chip enable 1 (SRAM) MCE1B IOEOB IOE1B RDB WRB NMIB I Read strobe Write strobe Non-maskable interrupt VAO-12 I/O External interrupt

Contextual Info: SHARP CORP biE ]> LH534P00 • aiao?« ooGiaao ost « s r p j CM O S 4M 512K x 8 / 256K x 16 Mask-Programmable ROM PIN CONNECTIONS FEATURES • • 524,288 x 8 bit organization (Byte mode) 262,144 x 16 bit organization (Word mode) 40-PIN DIP TOP VIEW

PSEUDO SRAM

Abstract: sharp mask rom
Contextual Info: MEMORIES SF-ASIC 8F-A8IC RAM ★Underdevelopment SF-ASIC RAM is a newly conceptualized memory device developed by Sharp. It allows users to mask any address region within the memory area at the users' wish. The device can also be used A D D R E S S M AP as a conventional Pseudo SRAM, as the device

K32I

Abstract: lhmn5
Contextual Info: SHARP SPEC No. I M R 9 5 4 0 7 ISSUE: Apr. 24 1995 To ; 1PRELIMINANY[ S P E C I F I C Product Type_ 3 2 M b i t A T Mask I O N S ROM LH M N 5Fxx Model No. L H 5 3 3 2 6 0 0 I ntThis specifications contains 3 pages including the cover and appendix.

Contextual Info: SHARP 1SPEC No. 1 M R 9 6 3 0 6 I SSUE: lsr.29 1996 To ; PRELIMINARY S P E C I F Product Type 16M 1CAT IONS b it MASK ROM L H 5 G 7 P x x LH53FV16P00AT-X SKThis specifications contains 9 paces including tbs cover. I f yon have aay objections, please contact us l*fore issuing purchasing order.