SDRAM TI -55 125 Search Results

UG532S7448JC-PL

Abstract: DD101
Contextual Info: UG532S7448JC Data sheets can be downloaded at www.unigen.com 256M Bytes 32M x 72 bits SYNCHRONOUS DRAM MODULE PC100-COMPATIBLE SDRAM Unbuffered DIMM based on 18 pcs 16M x 8 SDRAM with LVTTL, 4 banks & 4K Refresh FEATURES -0.3 to + 4.6V 0 to + 70°C -55°C to + 125°C

UG532S7448JJ-PL

Abstract: UG532S7448JJ UG532S7448JJ-PH
Contextual Info: UG532S7448JJ Data sheets can be downloaded at www.unigen.com 256M Bytes 32M x 72 bits SYNCHRONOUS DRAM MODULE PC100-COMPATIBLE SDRAM Unbuffered DIMM based on 18 pcs 16M x 8 SDRAM with LVTTL, 4 banks & 4K Refresh FEATURES -0.3 to + 4.6V 0 to + 70°C -55°C to + 125°C

81117822

Contextual Info: November 1996 Revision 2.0 FUJITSU DATA SHEET - SD C2U V7282 A -(6 7/84/100/125) T-S 16MByte (2M x 72) CMOS Synchronous DRAM Module - ECC General Description The SDC2UV7282(A)-(67/84/100/125)T-S is a high performance, 16-megabtye synchronous, dynamic RAM module organized

TM4TT64KPN-8A

Abstract: TM4TT64KPN TM8TT64KPN
Contextual Info: TM4TT64KPN 4ā194ā304 BY 64ĆBIT TM8TT64KPN 8ā388ā608 BY 64ĆBIT SYNCHRONOUS DYNAMIC RAM MODULES SMMS699A − MARCH 1998 − REVISED AUGUST 1998 D D D D D D D D High-Speed, Low-Noise Low-Voltage TTL − TM4TT64KPN . . . 4 194 304 x 64-Bits − TM8TT64KPN . . . 8 388 608 × 64 Bits

TM4SK64KPN

Abstract: TM8SK64KPN TMS664164 1tm4
Contextual Info: TM4SK64KPN 4ā194ā304 BY 64ĆBIT TM8SK64KPN 8ā388ā608 BY 64ĆBIT SYNCHRONOUS DYNAMIC RAM MODULES Ċ SODIMM SMMS709 − APRIL 1998 D D D D D D D D High-Speed, Low-Noise, Low-Voltage TTL − TM4SK64KPN . . . 4 194 304 x 64 Bits − TM8SK64KPN . . . 8 388 608 x 64 Bits

TM16TT64JPN

Abstract: TM16TT72JPN TM8TT64JPN TM8TT72JPN TMS664814
Contextual Info: TM8TT64JPN, TM16TT64JPN TM8TT72JPN, TM16TT72JPN SYNCHRONOUS DYNAMIC RAM MODULES SMMS700A − APRIL 1998 − REVISED AUGUST 1998 D D D D D D D D Single 3.3-V Power Supply − TM8TT64JPN . . . 8 388 608 x 64 Bits − TM16TT64JPN . . . 16 777 216 × 64 Bits

TMS626812ADGE

Abstract: TM2SR72EPN TM4SR72EPN TMS626812A TMS626812
Contextual Info: TM2SR72EPN 2ā097ā152 BY 72ĆBIT TM4SR72EPN 4ā194ā304 BY 72ĆBIT SYNCHRONOUS DYNAMIC RAM MODULES SMMS698A − JUNE 1997 − REVISED FEBRUARY 1998 D Organization D D D D D D D High-Speed, Low-Noise Low-Voltage TTL − TM2SR72EPN . . . 2 097 152 x 72 Bits

Contextual Info: < p August 1996 Revision 1.0 HATA GHFFT - SOB1UV6412- 67/84/100/125 T-S 8MByte (1Mx64) CMOS Synchronous DRAM Module General Description The SO B1UV6412-(67/84/100/125)T-S is a high performance, 8-megabtye synchronous, dynamic RAM module organized as 1 M

TM4TR64EPH8A

Abstract: TM2TR64EPH TM2TR72EPH TM4TR64EPH TM4TR72EPH TMS626812B TMS626812
Contextual Info: TM2TR64EPH, TM4TR64EPH TM2TR72EPH, TM4TR72EPH SYNCHRONOUS DYNAMIC RAM MODULES SMMS702B − JANUARY 1998 − REVISED APRIL 1998 D Organization: D D D D D D D D D JEDEC 168-Pin Dual-In-Line Memory − TM2TR64EPH . . . 2 097 152 x 64 Bits − TM4TR64EPH . . . 4 194 304 x 64 Bits

TM4SP64KPN

Abstract: TM8SP64KPN 10H14
Contextual Info: TM4SP64KPN 4ā194ā304 BY 64ĆBIT TM8SP64KPN 8ā388ā608 BY 64ĆBIT SYNCHRONOUS DYNAMIC RAM MODULES SMMS708 − APRIL 1998 D D D D D D D D High-Speed, Low-Noise, Low-Voltage TTL − TM4SP64KPN . . . 4 194 304 x 64 Bits − TM8SP64KPN . . . 8 388 608 x 64 Bits

TM2SR72EPH

Abstract: TM4SR72EPH TMS626812B TMS626812
Contextual Info: TM2SR72EPH 2ā097ā152 BY 72ĆBIT TM4SR72EPH 4ā194ā304 BY 72ĆBIT SYNCHRONOUS DYNAMIC RAM MODULES SMMS705A − FEBRUARY 1998 − REVISED APRIL 1998 D Organization D D D D D D D High-Speed, Low-Noise Low-Voltage TTL − TM2SR72EPH . . . 2 097 152 x 72 Bits

TM2SN64EPH

Abstract: TM4SN64EPH TMS626812B TM4SN64EPH10 TMS626812
Contextual Info: TM2SN64EPH 2ā097ā152 BY 64ĆBIT TM4SN64EPH 4ā194ā304 BY 64ĆBIT SYNCHRONOUS DYNAMIC RAM MODULES SMMS706A − MARCH 1998 − REVISED APRIL 1998 D Organization: D D D D D D D D High-Speed, Low-Noise, Low-Voltage TTL − TM2SN64EPH . . . 2 097 152 x 64 Bits

TM4SK64KPU

Abstract: TM8SK64KPU TMS664164
Contextual Info: TM4SK64KPU 4ā194ā304 BY 64ĆBIT TM8SK64KPU 8ā388ā608 BY 64ĆBIT SYNCHRONOUS DYNAMIC RAM MODULES Ċ SODIMM SMMS691A − AUGUST 1997 − REVISED NOVEMBER 1997 D D D D D D D D High-Speed, Low-Noise Low-Voltage TTL − TM4SK64KPU . . . 4 194 304 x 64 Bits

TMS626812ADGE

Abstract: TM2CN64EFN TM4CN64EFN TMS626812A TMS626812
Contextual Info: TM2CN64EFN 2ā097ā152 BY 64ĆBIT TM4CN64EFN 4ā194ā304 BY 64ĆBIT SYNCHRONOUS DYNAMIC RAM MODULES SMMS714 − MAY 1998 D D D D D D D D High-Speed, Low-Noise, Low-Voltage TTL − TM2CN64EFN . . . 2 097 152 x 64 Bits − TM4CN64EFN . . . 4 194 304 x 64 Bits

TM16LR64JFN

Abstract: TM8LR64JFN TMS664814
Contextual Info: TM8LR64JFN 8 388 608 BY 64ĆBIT TM16LR64JFN 16 777 216 BY 64ĆBIT SYNCHRONOUS DYNAMIC RAM MODULES SMMS710 − MAY 1998 D D D D D D D D High-Speed, Low-Noise, Low-Voltage TTL − TM8LR64JFN . . . 8 388 608 x 64 Bits − TM16LR64JFN . . . 16 777 216 × 64 Bits

TM8SK64JPN

Abstract: TMS664814
Contextual Info: TM8SK64JPN 8ā388ā608 BY 64ĆBIT SYNCHRONOUS DYNAMIC RAM MODULE Ċ SODIMM SMMS717 − JULY 1998 D Organization: D D D D D D D D Read Latencies 2 and 3 Supported D Support Burst-Interleave and − TM8SK64JPN . . . 8 388 608 x 64 Bits Single 3.3-V Power Supply

Contextual Info: CDC2509C 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS620 – DECEMBER 1998 D D D D D D D D D D D D D D PW PACKAGE TOP VIEW Designed to Meet PC SDRAM Registered DIMM Design Support Document Rev. 1.2 Spread Spectrum Clock Compatible Operating Frequency 25 MHz to 125 MHz

CDC2510A

Contextual Info: CDC2510C 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS621 – DECEMBER 1998 D D D D D D D D D D D D D PW PACKAGE TOP VIEW Designed to Meet PC SDRAM Registered DIMM Design Support Document Rev. 1.2 Spread Spectrum Clock Compatible Operating Frequency 25 MHz to 125 MHz

TMS626812

Abstract: TM2SJ64EPU
Contextual Info: TM2SJ64EPU 2ā097ā152 BY 64ĆBIT SYNCHRONOUS DYNAMIC RAM MODULES Ċ SODIMM SMMS687B − AUGUST 1997 − REVISED FEBRUARY 1998 D Organization: 2 097 152 x 64 Bits D Single 3.3-V Power Supply D Support Burst-Interleave and D ±10% Tolerance D Designed for 66-MHz 4-Clock Systems

CDC2509

Abstract: CDC2510A CDC2509A CDC2509B CDC2510B
Contextual Info: Understanding the Differences Between the CDC2509x/10x Devices Application Brief January 1999 Mixed Signal Linear Products SCAA040 IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue

TM8SK64JPU

Abstract: TMS664814
Contextual Info: TM8SK64JPU 8ā388ā608 BY 64ĆBIT SYNCHRONOUS DYNAMIC RAM MODULE Ċ SODIMM SMMS690B − AUGUST 1997 − REVISED FEBRUARY 1998 D Organization: D D D D D D D D Read Latencies 2 and 3 Supported D Support Burst-Interleave and − TM8SK64JPU . . . 8 388 608 x 64 Bits

TMS626812

Abstract: TM2SN64EPU TM4SN64EPU
Contextual Info: TM2SN64EPU 2ā097ā152 BY 64ĆBIT TM4SN64EPU 4ā194ā304 BY 64ĆBIT SYNCHRONOUS DYNAMIC RAM MODULES SMMS681 − AUGUST 1997 D Organization: D D D D D D D D High-Speed, Low-Noise Low-Voltage TTL − TM2SN64EPU . . . 2 097 152 x 64 Bits − TM4SN64EPU . . . 4 194 304 x 64 Bits

TMS626812ADGE

Abstract: TM2SN64EPN TM4SN64EPN TMS626812A
Contextual Info: TM2SN64EPN 2ā097ā152 BY 64ĆBIT TM4SN64EPN 4ā194ā304 BY 64ĆBIT SYNCHRONOUS DYNAMIC RAM MODULES SMMS696 − AUGUST 1997 D D D D D D D D High-Speed, Low-Noise Low-Voltage TTL − TM2SN64EPN . . . 2 097 152 x 64 Bits − TM4SN64EPN . . . 4 194 304 x 64 Bits

TM4SP64KPU

Abstract: TM8SP64KPU TMS664164
Contextual Info: TM4SP64KPU 4ā194ā304 BY 64ĆBIT TM8SP64KPU 8ā388ā608 BY 64ĆBIT SYNCHRONOUS DYNAMIC RAM MODULES SMMS689 − AUGUST 1997 D D D D D D D D High-Speed, Low-Noise Low-Voltage TTL − TM4SP64KPU . . . 4 194 304 x 64 Bits − TM8SP64KPU . . . 8 388 608 x 64 Bits