g5d2
Abstract: ths730a PM10-24S05 backplane layout SN74GTLPH1655 LT1083
Text: GTLP Evaluation Module EVM User’s Guide June 2001 Standard Linear & Logic Printed in U.S.A. 0601 SCEA023 GTLP Evaluation Module (EVM) User’s Guide SCEA023 June 2001 Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products
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SCEA023
E7E6E5E4E3E21
D9D8D7D6D5D4D3D2D11
g5d2
ths730a
PM10-24S05
backplane layout
SN74GTLPH1655
LT1083
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msi 7267 MOTHERBOARD SERVICE MANUAL
Abstract: ttl cookbook msi ms 7267 MOTHERBOARD CIRCUIT diagram "0.4mm" bga "ball collapse" height PCF 799 crystal oscillator 8MHz 4 pins smd diode MARKING F5 44C smd TRANSISTOR code marking A7 terminals diagram of smd transistor bo2 cookbook for ic 555
Text: GTL/GTLP Logic High-Performance Backplane Drivers Data Book Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information
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GDFP1-F48
-146AA
GDFP1-F56
-146AB
msi 7267 MOTHERBOARD SERVICE MANUAL
ttl cookbook
msi ms 7267 MOTHERBOARD CIRCUIT diagram
"0.4mm" bga "ball collapse" height
PCF 799
crystal oscillator 8MHz 4 pins
smd diode MARKING F5 44C
smd TRANSISTOR code marking A7
terminals diagram of smd transistor bo2
cookbook for ic 555
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SCEA026
Abstract: 784C P6245 SN74ABT244 SN74GTL1655 SN74GTLPH1655 SN74LVT244A SN74VMEH22501 VMEH22501 TDS500
Text: Application Report SCEA026 - February 2002 Logic in Live-Insertion Applications With a Focus on GTLP Jose M. Soltero and Ernest Cox Standard Linear & Logic ABSTRACT Live-insertion capability is an essential part of today’s high-speed data systems because
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SCEA026
784C
P6245
SN74ABT244
SN74GTL1655
SN74GTLPH1655
SN74LVT244A
SN74VMEH22501
VMEH22501
TDS500
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Signal path designer
Abstract: No abstract text available
Text: SN74GTLP1395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES349C – JUNE 2001 – REVISED NOVEMBER 2001 D D D D D D D D D D D D TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes
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SN74GTLP1395
SCES349C
SN74GTLP1395PW
SN74GTLP1395PWR
SN74GTLP1395
SCEM204,
Signal path designer
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SN74FB2033K
Abstract: No abstract text available
Text: SN74FB2033K 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS472G – MAY 1994 – REVISED SEPTEMBER 2001 D D D D Compatible With IEEE Std 1194.1-1991 BTL TTL A Port, Backplane Transceiver Logic (BTL) B Port Open-Collector B-Port Outputs Sink 100 mA BIAS VCC Pin Minimizes Signal Distortion
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SN74FB2033K
SCBS472G
SN74FB2033KRC
SN74FB2033KRCR
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Signal path designer
Abstract: No abstract text available
Text: SN74GTLP21395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES350C – JUNE 2001 – REVISED NOVEMBER 2001 D D D D D D D D D D D D D TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes
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SN74GTLP21395
SCES350C
SN74GTLP21395PWR
SN74GTLP21395
SCEM297,
SN74GTLP21395,
Signal path designer
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SN74GTL1655
Abstract: SN74GTLPH1655 SN74GTLPH1655DGGR Higgs 3
Text: Application Report SZZA016B - June 2001 Basic Design Considerations for Backplanes Shankar Balasubramaniam, Ramzi Ammar, Ernest Cox, Steve Blozis, and Jose M. Soltero Standard Linear & Logic ABSTRACT This application report describes design issues relevant to the parallel backplanes typically
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SZZA016B
SN74GTL1655
SN74GTLPH1655
SN74GTLPH1655DGGR
Higgs 3
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Untitled
Abstract: No abstract text available
Text: SN54GTL16612, SN74GTL16612 18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS SCBS480K – JUNE 1994 – REVISED AUGUST 2001 D D D D D D D D D D Members of Texas Instruments’ Widebus Family UBT Transceivers Combine D-Type Latches and D-Type Flip-Flops for
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SN54GTL16612,
SN74GTL16612
18-BIT
SCBS480K
5962-9689001QXA
SNJ54GTL16612WD
5962View
9689001QXA
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Untitled
Abstract: No abstract text available
Text: SN74FB2040 8-BIT TTL/BTL TRANSCEIVER SCBS173N – NOVEMBER 1991 – REVISED MARCH 2002 D D D D Compatible With IEEE Std 1194.1-1991 BTL TTL A Port, Backplane Transceiver Logic (BTL) B Port Open-Collector B-Port Outputs Sink 100 mA D D High-Impedance State During Power Up
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SN74FB2040
SCBS173N
24FB2040RC
SN74FB2040RCR
SN74FB2040
SCBM023B,
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Untitled
Abstract: No abstract text available
Text: SN74FB2033A 8-BIT TTL/BTL REGISTERED TRANSCEIVER SCBS174M – NOVEMBER 1991 – REVISED SEPTEMBER 2001 D D D D D Compatible With IEEE Std 1194.1-1991 BTL TTL A Port, Backplane Transceiver Logic (BTL) B Port Open-Collector B-Port Outputs Sink 100 mA BIAS VCC Pin Minimizes Signal Distortion
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SN74FB2033A
SCBS174M
SN74FB2033ARC
SN74FB2033ARCR
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SN74FB2041A
Abstract: No abstract text available
Text: SN74FB2041A 7-BIT TTL/BTL TRANSCEIVER SCBS172M – NOVEMBER 1991 – REVISED MARCH 2002 D D D D D Compatible With IEEE Std 1194.1-1991 BTL TTL A Port, Backplane Transceiver Logic (BTL) B Port Open-Collector B-Port Outputs Sink 100 mA BIAS VCC Pin Minimizes Signal Distortion
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SN74FB2041A
SCBS172M
28041ARC
SN74FB2041ARCR
SN74FB2041A
SCBM025B,
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Untitled
Abstract: No abstract text available
Text: SN74FB2031 9-BIT TTL/BTL ADDRESS/DATA TRANSCEIVER SCBS176N – NOVEMBER 1991 – REVISED JUNE 2001 D D D D D Compatible With IEEE Std 1194.1-1991 BTL TTL A Port, Backplane Transceiver Logic (BTL) B Port Open-Collector B-Port Outputs Sink 100 mA High-Impedance State During Power Up
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SN74FB2031
SCBS176N
39TATUS
SN74FB2031RC
SN74FB2031RCR
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Untitled
Abstract: No abstract text available
Text: SN74GTLP817 GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER SCES285E – OCTOBER 1999 – REVISED AUGUST 2001 D D D D D D D D D D D D DGV, DW, OR PW PACKAGE TOP VIEW OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP
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SN74GTLP817
SCES285E
SN74GTLP817PWR
SN74GTLP817
SCEM187,
SCEJ119,
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Signal path designer
Abstract: cpci backplane schematic
Text: SN74GTLP1394 2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES286E – OCTOBER 1999 – REVISED AUGUST 2001 D D D D D D D D D D D D D, DGV, OR PW PACKAGE TOP VIEW TI-OPC Circuitry Limits Ringing on
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SN74GTLP1394
SCES286E
SN74GTLP1394RGYR
SN74GTLP1394
SCEM188A,
SCEJ118,
SN74GTLP1394,
Signal path designer
cpci backplane schematic
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