P2S3
Abstract: SGDA DS440 Scatter-Gather
Text: DS440 April 24, 2009 Channelized Direct Memory Access and Scatter Gather v1.00a Product Specification Introduction LogiCORE IP Facts This specification is for a DMA Scatter Gather controller which can scale up to a relatively large number of channels (hundreds). Many concepts from
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DS440
P2S3
SGDA
Scatter-Gather
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Scatter-Gather direct memory access SG-DMA
Abstract: memory access (DMA) controller Scatter-Gather CRC-32 QII55003-7 constructs
Text: 5. Scatter-Gather DMA Controller Core QII55003-7.1.0 Core Overview The Scatter-Gather direct memory access SG-DMA controller core implements high-speed data transfer between two devices. The SG-DMA core can be used to transfer data from: • ■ ■ memory to memory
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QII55003-7
Scatter-Gather direct memory access SG-DMA
memory access (DMA) controller
Scatter-Gather
CRC-32
constructs
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LFE3-95EA-7FN672CES
Abstract: Scatter-Gather wishbone interface wishbone HB1009 modelsim SE 6.3f user guide IPUG67
Text: Scatter-Gather Direct Memory Access Controller IP Core User’s Guide October 2010 IPUG67_01.6 Table of Contents Chapter 1. Introduction . 4
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IPUG67
LFXP2-40E-6F672C
LFXP2-40E-6F672C
D-2009
12L-1.
LFE3-95EA-7FN672CES
Scatter-Gather
wishbone interface
wishbone
HB1009
modelsim SE 6.3f user guide
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Scatter-Gather example
Abstract: Scatter-Gather
Text: Accelerating Functions with the C2H Compiler: Scatter-Gather DMA with Checksum July 2006, Version 1.1 Application Note 417 Introduction The Nios II C-to-Hardware Acceleration C2H Compiler is a powerful tool that generates hardware accelerators for software functions. This application note uses the C2H Compiler to map C code for a scatter-gather direct
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Untitled
Abstract: No abstract text available
Text: Preliminary PowerPC 405CR Embedded Controller Data Sheet Features • PowerPCTM 405 32-bit RISC processor core operating up to 200 MHz • DMA support for external peripherals, internal UART and memory - Memory Management Unit - Scatter-gather chaining supported
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405CR
32-bit
PC-100
40-bit
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TS6 v14
Abstract: No abstract text available
Text: Preliminary PowerPC 405CR Embedded Controller Data Sheet Features • IBM PowerPCTM 405 32-bit RISC processor core operating up to 266MHz • DMA support for external peripherals, internal UART and memory - Memory Management Unit - Scatter-gather chaining supported
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405CR
32-bit
266MHz
PC-100
133MHz
40-bit
SA14-2522-01
TS6 v14
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TS6 v14
Abstract: 405CR frequency-266MHz
Text: Preliminary PowerPC 405CR Embedded Controller Data Sheet Features • IBM PowerPCTM 405 32-bit RISC processor core operating up to 266MHz • DMA support for external peripherals, internal UART and memory - Memory Management Unit - Scatter-gather chaining supported
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405CR
32-bit
266MHz
PC-100
133MHz
40-bit
SA14-2522-01
TS6 v14
frequency-266MHz
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4413C
Abstract: No abstract text available
Text: LAN9420/LAN9420i Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface PRODUCT FEATURES Datasheet Highlights Optimized for embedded applications with 32-bit RISC CPUs Integrated descriptor based scatter-gather DMA and
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LAN9420/LAN9420i
32-bit
LAN9420/LAN9420i
128-VTQFP
4413C
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Untitled
Abstract: No abstract text available
Text: LAN9420/LAN9420i Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface PRODUCT FEATURES Datasheet Highlights Optimized for embedded applications with 32-bit RISC CPUs Integrated descriptor based scatter-gather DMA and
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LAN9420/LAN9420i
32-bit
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LAN9420
Abstract: 128-PIN CRC-16 IEC61249-2-21
Text: LAN9420/LAN9420i Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface PRODUCT FEATURES Datasheet Highlights Optimized for embedded applications with 32-bit RISC CPUs Integrated descriptor based scatter-gather DMA and
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LAN9420/LAN9420i
32-bit
32-bit,
33MHz,
300uW.
LAN9420
128-PIN
CRC-16
IEC61249-2-21
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BA1 K19
Abstract: BA1K19 IBM25PPC405CR-3BC200C PPC405CR PowerPC EBC 405CR PPC405 SA-12E PowerPC 405CR PPC405 IBM
Text: PowerPC 405CR Embedded Processor Data Sheet Features • IBM PowerPC 405 32-bit RISC processor core operating up to 266MHz - Memory Management Unit - 16KB instruction and 8KB data caches - Scatter-gather chaining supported - Four channels • Programmable Interrupt Controller supports
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405CR
32-bit
266MHz
PC-133
133MHz
40-bit
SA14-2522-08
BA1 K19
BA1K19
IBM25PPC405CR-3BC200C
PPC405CR
PowerPC EBC
PPC405
SA-12E
PowerPC 405CR
PPC405 IBM
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100n x2 pme 285 mb
Abstract: IP100A IP100ALF 2N2905 transistor 100BASE-FX 100N 93C46 0090C3 TFD65 "network interface cards"
Text: IP100A LF Preliminary Data Sheet Integrated 10/100 Ethernet MAC + PHY Features General Description Single chip 10/100BASE, half or full duplex Ethernet Media Access Controller IEEE 802.3 compliant 100BASE-TX/100BASE-FX/10BASE-T PCI Bus master scatter/gather DMA on any
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IP100A
10/100BASE,
100BASE-TX/100BASE-FX/10BASE-T
LF-DS-R17
100n x2 pme 285 mb
IP100ALF
2N2905 transistor
100BASE-FX
100N
93C46
0090C3
TFD65
"network interface cards"
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LAN9420
Abstract: LAN9420i EPC TRANSFORMER 128-PIN AD10 CRC-16 jumbo led
Text: LAN9420/LAN9420i Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface PRODUCT FEATURES Datasheet Highlights Optimized for embedded applications with 32-bit RISC CPUs Integrated descriptor based scatter-gather DMA and
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32-bit
32-bit,
33MHz,
LAN9420
LAN9420i
EPC TRANSFORMER
128-PIN
AD10
CRC-16
jumbo led
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TS6 v14
Abstract: IBM CoreConnect bus
Text: PowerPC 405CR Embedded Processor Data Sheet Features • IBM PowerPC 405 32-bit RISC processor core operating up to 266MHz - Memory Management Unit - 16KB instruction and 8KB data caches - Scatter-gather chaining supported - Four channels • Programmable Interrupt Controller supports
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405CR
32-bit
266MHz
133MHz
40-bit
SA14-2522-09
TS6 v14
IBM CoreConnect bus
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IBM25PPC405CR-3BC200C
Abstract: RISCwatch Trace IBM J9 405CR PC-100 PPC405 PPC405CR SA12E ppc405 BSDL
Text: PowerPC 405CR Embedded Controller Data Sheet Features • IBM PowerPCTM 405 32-bit RISC processor core operating up to 266MHz • DMA support for external peripherals, internal UART and memory - Memory Management Unit - Scatter-gather chaining supported - 16KB instruction and 8KB data caches
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405CR
32-bit
266MHz
PC-100
133MHz
SA14-2522-05
IBM25PPC405CR-3BC200C
RISCwatch Trace
IBM J9
PPC405
PPC405CR
SA12E
ppc405 BSDL
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ppc405 BSDL
Abstract: No abstract text available
Text: PowerPC 405CR Embedded Controller Data Sheet Features • IBM PowerPCTM 405 32-bit RISC processor core operating up to 266MHz • DMA support for external peripherals, internal UART and memory - Memory Management Unit - Scatter-gather chaining supported - 16KB instruction and 8KB data caches
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405CR
32-bit
266MHz
PC-100
133MHz
40-bit
SA14-2522-02
ppc405 BSDL
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communication between cpu and iop
Abstract: RISCwatch schema SCHEMAT 480R 480RDK bus arbiter "network interface cards"
Text: IOP 480 Features • PowerPC 32-Bit RISC CPU Core with MMU, 4KB I-Cache and 2KB D-Cache v2.2 Compliant 32-Bit 33MHz Controller with Two Block Mode or Scatter/Gather DMA Channels which allow unlimited bursts up to 132Mbytes/Second Processor ■ PCI ■ CompactPCI
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32-Bit
32-Bit
33MHz
132Mbytes/Second
66MHz
480-SIL-PB-P1-02
communication between cpu and iop
RISCwatch
schema
SCHEMAT
480R
480RDK
bus arbiter
"network interface cards"
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communication between cpu and iop
Abstract: low cost processor PLX 480 Programmable interval timer chips "network interface cards"
Text: IOP 480 Highlights • PowerPC 32-Bit RISC CPU Core with MMU, 4KB I-Cache and 2KB D-Cache ■ Performance up to 70 MIPS @ 66MHz ■ PCI v2.2 Compliant 32-Bit 33MHz Controller with Two Block Mode or Scatter/Gather DMA Channels which allow unlimited bursts up to
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32-Bit
66MHz
32-Bit
33MHz
132Mbytes/Second
256Mbytes
66MHz
480-SIL-PB-0-1
communication between cpu and iop
low cost processor
PLX 480
Programmable interval timer chips
"network interface cards"
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CRC-10
Abstract: MXT3010
Text: Planning for, and upgrading to, the MXT3020C Applications Note #18 Revision 3.0 - 14 July 1998 Order Number: 100388-03 Maker Communications 73 Mount Wayte Avenue Framingham, MA 01702 April 1998 Copyright c 1998 by Maker Communications, Inc. All rights reserved.
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MXT3020C
MXT3020
MXT3020C:
CRC-10
MXT3010
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semiconductor manual reference
Abstract: gather capacitor MXT3010 DECchip 21140 FTC 380 manual R50BC MOVER+592.+T.+X1.+00
Text: MXT3020 reference manual version 2.0 Order Number: 100107-02 Revision B of the MXT3020 November 1997 Copyright c 1997 by Maker Communications, Inc. All rights reserved. Printed in the United States of America. The information in this document is believed to be correct, however, the
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MXT3020
MXT3020
semiconductor manual reference
gather capacitor
MXT3010
DECchip 21140
FTC 380 manual
R50BC
MOVER+592.+T.+X1.+00
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TC6367
Abstract: CRC-10 MXT3010 MXT4400 486 motherboard schematic AS3010
Text: MXT3020 reference manual version 4.0 Order Number: 100107-04 Revision C of the MXT3020 July 1999 Copyright c 1999 by Maker Communications, Inc. All rights reserved. Printed in the United States of America. The information in this document is believed to be correct, however, the
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MXT3020
MXT3020
TC6367
CRC-10
MXT3010
MXT4400
486 motherboard schematic
AS3010
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fpga cdma ip vhdl examples
Abstract: DS792 AMBA AXI4 stream specifications xc6vlx240t XPS Central DMA cdma system implementation fpga cdma by vhdl examples
Text: LogiCORE IP AXI Central Direct Memory Access v3.02.a DS792 January 18, 2012 Product Specification Introduction LogiCORE IP Facts Table The Advanced eXtensible Interface Central Direct Memory Access (AXI CDMA) core is a soft Xilinx Intellectual Property (IP) core for use with the Xilinx
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DS792
fpga cdma ip vhdl examples
AMBA AXI4 stream specifications
xc6vlx240t
XPS Central DMA
cdma system implementation
fpga cdma by vhdl examples
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an3396
Abstract: MPC5500 Configuration and Initialization MPC5534 AN2864SW eMIOS channel is set up to drive the eTPU decimation MPC500 MPC5500 MPC5561 mpc5500r19
Text: Freescale Semiconductor Application Note Document Number: AN3396 Rev. 0, 01/2007 MPC5500: A Decimation Solution with Zero CPU Loading by: Geoff Emerson David McMenamin MCD Applications East Kilbride, Scotland 1 Introduction The MPC5500 microcontroller family provides a
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AN3396
MPC5500:
MPC5500
an3396
MPC5500 Configuration and Initialization
MPC5534
AN2864SW
eMIOS channel is set up to drive the eTPU
decimation
MPC500
MPC5561
mpc5500r19
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an3396
Abstract: MPC500 MPC5500 MPC5534 MPC5561 MPC5500 Configuration and Initialization eMIOS channel is set up to drive the eTPU emios
Text: Freescale Semiconductor Application Note MPC5500: A Decimation Solution with Zero CPU Loading by: Geoff Emerson David McMenamin MCD Applications East Kilbride, Scotland 1 Introduction The MPC5500 microcontroller family provides a flexible feature set enabling a wide range of automotive
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MPC5500:
MPC5500
MPC5534
an3396
MPC500
MPC5561
MPC5500 Configuration and Initialization
eMIOS channel is set up to drive the eTPU
emios
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