SCAA021 Search Results

TMS320C40

Abstract: TMS320C31 filtering SN74ACT3638 SN74ACT3641
Contextual Info: Optimizing DSPĆBased Digital Filtering Systems With ApplicationĆSpecific FIFOs Application Report 1994 Advanced System Logic Printed in U.S.A. 1194 – CP SCAA021 Template Release Date: 7–20–94 Optimizing DSPĆBased Digital Filtering Systems With ApplicationĆSpecific FIFOs

SN74ACT3631

Abstract: SN74ACT3641 SN74ACT3651 SN74ALVC3631 SN74ALVC3641 SN74ALVC3651
Contextual Info: SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 x 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A

SN74ACT3631

Abstract: SN74ACT3641 SN74ACT3651 SN74ALVC3631 SN74ALVC3641 SN74ALVC3651
Contextual Info: SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 x 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A

Contextual Info: SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 x 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A

Contextual Info: SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 x 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A

Contextual Info: SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 x 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A

Contextual Info: SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 x 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A

SN74ACT3631

Abstract: SN74ACT3641 SN74ACT3651 SN74ALVC3631 SN74ALVC3641 SN74ALVC3651
Contextual Info: SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 x 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A

Contextual Info: SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 x 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A

Contextual Info: SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 x 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A

SN74ACT3631

Abstract: SN74ACT3641 SN74ACT3651 SN74ALVC3651
Contextual Info: SN74ALVC3651 2048 x 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SDMS025A – OCTOBER 1999 – REVISED DECEMBER 1999 D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A to Port B Synchronous Read-Retransmit Capability

SN74ACT3631

Abstract: SN74ACT3641 SN74ACT3651 SN74ALVC3631 SN74ALVC3641 SN74ALVC3651
Contextual Info: SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 x 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A

Contextual Info: SN74ALVC3651 2048 x 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SDMS025 – OCTOBER 1999 D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A to Port B Synchronous Read-Retransmit Capability Mailbox Register in Each Direction

SN74ACT3631

Abstract: SN74ACT3641 SN74ACT3651 SN74ALVC3631 SN74ALVC3641 SN74ALVC3651 component drawing bqfp 132
Contextual Info: SN74ALVC3631, SN74ALVC3641, SN74ALVC3651 512 x 36, 1024 × 36, 2048 × 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SDMS025B – OCTOBER 1999 – REVISED JUNE 2000 D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A