SATELLITE A25 Search Results

AC27

Abstract: AF17 ZL50212 ZL50212GB
Contextual Info: ZL50212 288 Channel Voice Echo Canceller Data Sheet Features • • • • • • • • • • Voice over IP network gateways Voice over ATM, Frame Relay T1/E1/J1 multichannel echo cancellation Wireless base stations Echo Canceller pools DCME, satellite and multiplexer system

TDG 2003

Abstract: dta9 PCM AT5 dta7 tms echo cancellation zarlink modem E1 PCM encoder EVP8 LMS adaptive filter LMS adaptive Filters
Contextual Info: ZL50212 288 Channel Voice Echo Canceller Data Sheet Features • • • • • • • • • • Voice over IP network gateways Voice over ATM, Frame Relay T1/E1/J1 multichannel echo cancellation Wireless base stations Echo Canceller pools DCME, satellite and multiplexer system

motorola SG4

Abstract: AC27 AF17 ZL50212 ZL50212GB DTA3
Contextual Info: ZL50212 288 Channel Voice Echo Canceller Data Sheet Features • • • • • • • • • • Voice over IP network gateways Voice over ATM, Frame Relay T1/E1/J1 multichannel echo cancellation Wireless base stations Echo Canceller pools DCME, satellite and multiplexer system

T2M3

Contextual Info: ZL50212 288 Channel Voice Echo Canceller Data Sheet March 2003 Features • • • • • • • • • • Voice over IP network gateways Voice over ATM, Frame Relay T1/E1/J1 multichannel echo cancellation Wireless base stations Echo Canceller pools DCME, satellite and multiplexer system

J1455

Abstract: orbcomm E80050015 satellite IP modem Satellite modem Digi m10 E25050102 Digi International 810E board Satellite modem
Contextual Info: Digi m10 Technical Overview And Reference Date: 25 November 2009 90033936_A Copyright Notice Digi International has prepared this manual for the use of its employees, agents, and its customers. This manual contains proprietary information, which is protected by copyright.

Contextual Info: Digi m10 Technical Overview And Reference Date: 12 January 2012 90033936_C Copyright Notice Digi International has prepared this manual for the use of its employees, agents, and its customers. This manual contains proprietary information, which is protected by copyright.

L4998

Abstract: L9658 mb449 L9654 AN2357 ST30F7xx st30f MB467 ST L9654 ST10F252
Contextual Info: AN2357 Application note Connecting ST10F252 evaluation board to the airbag eva board Introduction The aim of this document is to provide the necessary information to implement the modifications to connect the ST airbag eva board MB467 to the ST10F252 evaluation

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        ! ! "# # Advance Version February 1999 2975 Stender Way, Santa Clara, California 95054 Telephone: 800 345-7015 • TWX: 910-338-2070 • FAX: (408) 492-8674

RC32300

Abstract: SPECIAL2 SDBBP IDT RC32334 Users Manual 79rc32334 IDT79RC32334
Contextual Info: IDT79RC32334 and IDT79RC32332 Integrated Communications Processors Y Revision RISCore 32300 Family User Reference Manual June 2002 2975 Stender Way, Santa Clara, California 95054 Telephone: (800) 345-7015 • TWX: 910-338-2070 • FAX: (408) 330-1748

RC32300

Abstract: c3233 ATMEL Packaging and labeling guideline MIPS r3000 RC32300 datasheet IDT RC32334 Users Manual jm 60 ac
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        !   "     November 2000 2975 Stender Way, Santa Clara, California 95054 Telephone: 800 345-7015 • TWX: 910-338-2070 • FAX: (408) 492-8674

test bench code for uart 16550

Abstract: X20C04J1
Contextual Info: IDT79S334A Evaluation Board Manual February 2001 2975 Stender Way, Santa Clara, California 95054 Telephone: 800 345-7015 • TWX: 910-338-2070 • FAX: (408) 330-1748 Printed in U.S.A. 2001 Integrated Device Technology, Inc. DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance

25256 eeprom

Abstract: st mem RC3041 RC32364 RC4640 S334A Uart project u2389 10UF-50V
Contextual Info: IDT79S334A Evaluation Board Manual February 2001 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: 800 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. 2005 Integrated Device Technology, Inc. DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance

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        ! ! "# # Version 1.0 March 1999 2975 Stender Way, Santa Clara, California 95054 Telephone: 800 345-7015 • TWX: 910-338-2070 • FAX: (408) 492-8674 Printed in U.S.A.

79RC32438

Abstract: IDT74FCT245 MIPS32 RC32438
Contextual Info: 79RC32438 IDTTM InterpriseTM Integrated Communications Processor Features Memory and Peripheral Device Controller – Provides “glueless” interface to standard SRAM, Flash, ROM, dual-port memory, and peripheral devices – Demultiplexed address and data buses: 16-bit data bus, 26-bit

Contextual Info: 79RC32438 IDTTM InterpriseTM Integrated Communications Processor ◆ Memory and Peripheral Device Controller – Provides “glueless” interface to standard SRAM, Flash, ROM, dual-port memory, and peripheral devices – Demultiplexed address and data buses: 16-bit data bus, 26-bit

RC32438

Abstract: 79RC32438 IDT74FCT245 MIPS32 MIPS32 instruction set
Contextual Info: 79RC32438 IDTTM InterpriseTM Integrated Communications Processor Features Memory and Peripheral Device Controller – Provides “glueless” interface to standard SRAM, Flash, ROM, dual-port memory, and peripheral devices – Demultiplexed address and data buses: 16-bit data bus, 26-bit

Contextual Info: 79RC32438 IDTTM InterpriseTM Integrated Communications Processor Features Memory and Peripheral Device Controller – Provides “glueless” interface to standard SRAM, Flash, ROM, dual-port memory, and peripheral devices – Demultiplexed address and data buses: 16-bit data bus, 26-bit

Satellite A25

Abstract: tl7705 BD 4908
Contextual Info: ,'76 6  YDOXDWLRQ %RDU G 0DQX DQXDO February 2001 2975 Stender Way, Santa Clara, California 95054 Telephone: (800 345-7015 • TWX: 910-338-2070 • FAX: (408) 330-1748 Printed in U.S.A. 2001 Integrated Device Technology, Inc. DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance

J4210

Abstract: DNA 1002 RC3041 RC32364 RC4640 test bench code for uart 16550 Satellite A25 SPI EEPROM 25256 md2533
Contextual Info: IDT79S332 Evaluation Board Manual February 2001 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: 800 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. 2005 Integrated Device Technology, Inc. DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance

AT697

Abstract: D2578 AT6014F 56 pin edac connector hasp AT49BV802A D3088 AT49BV802 AT697-EVAB pinout socket 754
Contextual Info: AT697 Evaluation Board . User Manual Section 1 Overview. 1-2 1.1 Features .1-2

RC32438

Abstract: 79RC32438 IDT74FCT245 MIPS32 OC26
Contextual Info: 79RC32438 IDTTM InterpriseTM Integrated Communications Processor Features Memory and Peripheral Device Controller – Provides “glueless” interface to standard SRAM, Flash, ROM, dual-port memory, and peripheral devices – Demultiplexed address and data buses: 16-bit data bus, 26-bit

Contextual Info: 79RC32438 IDTTM InterpriseTM Integrated Communications Processor Features Preliminary Information* EJTAG Debug Support – CPU control with start, stop and single stepping – Software breakpoints via the SDBBP instruction – Optional hardware breakpoints on virtual addresses; 4 instruction and 2 data breakpoints, 2 instruction and 1 data breakpoint, or no breakpoints

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      ! ! Version 1.1 November 1999 2975 Stender Way, Santa Clara, California 95054 Telephone: 800 345-7015 • TWX: 910-338-2070 • FAX: (408) 492-8674 Printed in U.S.A.

Contextual Info: 79RC32438 IDTTM InterpriseTM Integrated Communications Processor Features Preliminary Information* EJTAG Debug Support – CPU control with start, stop and single stepping – Software breakpoints via the SDBBP instruction – Optional hardware breakpoints on virtual addresses; 4 instruction and 2 data breakpoints, 2 instruction and 1 data breakpoint, or no breakpoints