S55303 Search Results

Contextual Info: SN74ALS229B 16 x 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SPAS09Q - MARCH 1990 - REVISED JUNE 1992 • Independent Asychronous Inputs and Outputs • 16 Words by 5 Bits • Data Rates From 0 to 40 MHz • Fall-Through Time. . . 14 ns "typ • 3-State Outputs

D3348

Abstract: 74AC11151
Contextual Info: 74AC11151 1-0F-8 DATA SELECTOR/MULTIPLEXER D3348, JUNE 1989 - REVISED APRIL 1993 * 8-Llne to 1-Llne Multiplexers Can Perform as Boolean Function Generators, Parallel-to-Serlal Converters, or Data Source Selectors * Flow-Through Architecture Optimizes PCB Layout

Contextual Info: SN54HC253, SN74HC253 DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS _ SCLS133A-DECEMBER 1982 - REVISED JANUARY 1996 3-State Version of 'HC153 High-Current Inverting Outputs Drive up to 15 LSTTL Loads

Contextual Info: 54AC11020,74AC11020 DUAL 4-INPUT POSITIVE-NAND GATES D2957, MAHCH 1987-REVISEDAPRIL1993 54AC11020. . . J PACKAGE 74AC11020. . . D OR N PACKAGE TOP VIEW * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations Minimize High-Speed Switching Noise

SN74LV08

Contextual Info: SN74LV08 QUADRUPLE 2-INPUT POSITIVE-AND GATE S C L S 1 86 A - FEBR UARY 1993 - REVISED JULY 1995 1 EPIC Enhanced-Performance Implanted CMOS 2-ji Process D, DB, OR PW PACKAGE CTOP VIEW) Typical V q l p (Output Ground Bounce) < 0.8 V at Vc c = 3.3 V, TA = 25°C

OmS430

Abstract: TLV2342 TLV2342ID TLV2342IDR TLV2342IP TLV2342IPWLE TLV2342Y
Contextual Info: TLV2342I, TLV2342Y LinCMOS LOW-VOLTAGE HIGH-SPEED DUAL OPERATIONAL AMPLIFIERS S L O S 1 1 4 - M A Y 1992 D OR P PACKAGE TOP VIEW] Wide Range of Supply Voltages Over Specified Temperature Range: -40°C to 85°C. . . 2 V to 8 V Fully Characterized at 3 V and 5 V

SN74LV125

Contextual Info: SN74LV125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES003A- NOVEMBER 1 9 9 4 - REVISED JULY 1996 D, DB, OR PW PACKAGE TOP VIEW • EPIC (Enhanced-Performance Implanted CMOS) 2-ii Process • Typical V q l p (Output Ground Bounce) < 0.8 V at VCc = 3.3 V, TA = 25°C

PVA c17

Abstract: FL-41 b24 b03 TLC5733 wj a75 TLC5733IPM
Contextual Info: TLC5733 20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER WITH HIGH-PRECISION CLAMP SLAS104-JULY 1995 3-Channel CMOS ADC 8-Bit Resolution Analog Input Bandwidth. . . >14 MHz Suitable for YUV or RGB Applications Digital Clamp Optimized for NTSC or PAL YUV Component

Contextual Info: 54AC11021,74AC11021 DUAL 4-INPUT POSITIVE-AND GATES _ D 2957, JULY 1987 - R EVISED APRIL 1993 * Flow-Through Architecture Optimizes PCB Layout 54AC11021 . . . J PACKAGE 74AC11021 . . . D OR N PACKAGE TOP VIEW * Center-Pin Vcc and GND Configurations

SN74ALVCH16952

Contextual Info: SN74ALVCH16952 16- BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCES011 - JULY 1995 DGG OR DL PACKAGE TOP VIEW 10EA B [ 1 1C L K A B [ 2 1CEAB [ 3 GND [ 4 1A1 [ 5 1A2 [ 6 vCc È 7 1A3 L 8 1A4 [ 9 1A5 [ 10 g n d [ 11 1A6 [ 12 1A7 [ 13 d e s c r ip t io n

74AC11646

Abstract: D2957
Contextual Info: 74AC11646 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS _ P2957, JULY 1987 - REVISED APRIL 1993 * Independent Registers for A and B Buses * Multiplexed Real-Time and Stored Data * Flow-Through Architecture Optimizes PCB Layout

D2525

Abstract: SN75160B SN75161B SN75162B
Contextual Info: SN75160B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER SLLS004A- D2525, OCTOBER 1 9 8 5 - REVISED FEBRUARY 1993 MEETS IEEE STANDARD 488-1978 GPIB DW OR N PACKAGE 8-Channel Bidirectional Transceiver (TOP VIEW) Power-Up/Power-Down Protection (Glitch Free)

tm001

Abstract: TM0010
Contextual Info: defining a degree of excellence T1 SURFACE MOUNT TRANSFORMER S553-0320-00 Bel introduces a T1 transformer designed to support the industry's aggressive price requirements, while remaining fit and function compatible to the industry standards. Carefully controlled internal

Centronic 36 package

Abstract: 17PM K011 04V applications of microprocessor in printer CONNECTOR CENTRONIC 34 pin TL16C550 54LS245 74LS245 TL16C450 TL16C452 TL16C550B
Contextual Info: TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO S L L S 18 9 B -N O V E M B E R 1994 - REVISED JUNE 1997 IBM PC/AT Compatible Programmable Serial Interface Characteristics for Each Channel: - 5-, 6-, 7-, or 8-Bit Characters - Even, Odd, or No Parity Bit Generation

ace dm he tv

Abstract: tda 1047 NS16550A TL16C450 TL16C550B
Contextual Info: TL16C550B ASYNCHRONOUS COMMUNICATIONS ELEMENT SLLS136A-JANUARY 1994- REVISED MARCH 1996 Capable of Running With All Existing TL16C450 Software After Reset, All Registers Are Identical to the TL16C450 Register Set In the FIFO Mode, Transmitter and Receiver

Contextual Info: TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL SLLÆ191B-JANUARY 1995-R EV ISE D MARCH 1996 • Pin-to-PIn Compatible With the Existing TL16C550B/C • Programmable 16- or 64-Byte FIFOs to Reduce CPU Interrupts • Programmable Auto-RTS and Auto-CTS

Contextual Info: SN54AHCT14, SN74AHCT14 HEX SCHMITT-TRIGGER INVERTERS SCLS246B - OCTOBER 1985 - REVISED MARCH 1996 Inputs Are TTL-Voltage Compatible EPIC"4 Enhanced-Performance Implanted CMOS Process SN54AHCT14 . . . J OR W PACKAGE SN74AHCT14 . . . D, DB, N, OR PW PACKAGE

tlc1540cn

Abstract: TlC1540 TLC1540CFN
Contextual Info: TLC1540C, TLC1541C 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS073A- DECEMBER 1985 - REVISED MARCH 1985 • 10-Bit Resolution A/D Converter • Microprocessor Peripheral or Stand-Alone Operation • On-Chip 12-Channel Analog Multiplexer

000E-12

Contextual Info: TLE2161, TLE2161A, TLE2161B EXCALIBUR JFET-INPUT HIGH-OUTPUT-DRIVE jiPOWER OPERATIONAL AMPLIFIERS D3371, N O VEM BER 1 9 8 9 - REVISED FEBR UARY 1991 available features Excellent Output Drive Capability Vq = ± 2.5 V Min at Rl = 100 £2, VCC± = ± 5 V V0 = ± 12-5 V Min at Rl = 600 Î2,

6S30S

Contextual Info: SN54LVT646, SN74LVT646 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS I SCBS140D- MAY 1992- REVISED JULY 1995 SN54LVT646. . . JT OR W PACKAGE SN74LVT646 . . . DB, DW, OR PW PACKAGE {TOP VIEW State-of-the-Art Advanced BICMOS Technology ABT) Design for 3.3-V

SN75129

Abstract: 1N3064 SN75128
Contextual Info: SN75128, SN75129 EIGHT-CHANNEL LINE RECEIVERS SLLS076A- D2305, JANUARY 1977 - REVISED MARCH 1993 N PACKAGE Meets IBM 360/370 I/O Specification TOP VIEW Input Resistance. . . 7 k£2 to 20 kQ 1S/1 S t [ 1 1A [ 2 Output Compatible With TTL Schottky-Clamped Transistors

EIA-485

Abstract: SN65LBC172 SN75172 SN75LBC172 SN75LBC173 SN75LBC175
Contextual Info: SN65LBC172, SN75LBC172 QUADRUPLE LOW-POWER DIFFERENTIAL LINE DRIVER SLLS163-JULY 1993 • • • • N PACKAGE [TOP VIEW Meet or Exceed EIA Standard RS-485 Designed for High-Speed Multipoint Transmission on Long Bus Lines in Noisy Environments Support Data Rates up to and Exceeding

SN74AHCT374

Contextual Info: SN74AHCT374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCLS241 - O CTO BER 1995 DB, DW, N, OR PW PACKAGE c ro p v ie w Inputs Are TTL-Voltage Compatible EPIC Enhanced-Performance Implanted CMOS) Process Package Options Include Plastic

SN74ACT8994

Contextual Info: g 1992 SN54ACT8994, SN74ACT8994 DIGITAL BUS MONITORS SCASI96-03604, JULY 1990-REVISED MARCH 1992 Cascaded PSA Mode Allows Compression of Parallel Data Paths Greater Than 16 Bits In Width Direct Memory Access DMA Speeds Memory and Register File Read/Wrtte