RK 74A Search Results

Signal Generators

Abstract: RC lowpass digital clock diagram digital clock circuit diagram
Contextual Info: IM R RK Semiconductor HI5905EVAL2 Evaluation Board User’s Manual A p p lic a tio n Note J n n u n r y 1999 Description The HI5905EVAL2 evaluation board allows the circuit designer to evaluate the performance of the Harris HI5905 monolithic 14-bit 5 MSPS analog-to-digital converter ADC .

Contextual Info: fg ] H ig h - S p e e d CM O S 8 - B it R e g is te r w it h Quality q s 5 4 / 7 4 f c t 37 7 t q s 5 4 /7 4 fc t2 3 7 7 t P ln rk Fnahlp S e m ic o n d u c t o r , I n c . FEATURES/BENEFITS DESCRIPTION • Pin and function compatible to the 74F377 74FCT377 and 74ABT377

87CM74

Abstract: TLCS-870 TMP87 TMP87CH74AF TMP87CM74AF TMP87PM74F sp00a 87CH74-149 87CH74
Contextual Info: TOSHIBA TMP87CH74A/M74A CMOS 8 b f ' y h V ' f ? n = l > h n - 7 TM P87CH74AF, TM P87CM 74AF h A/D n > /s' - 9 , 87CH74A/M74AÜ, 9 y 9 ï $ X Tf27fcffà<D§è$è\B\ì&fJ: £' & Ñ Ü L f z FlbiS, F l¡ftifb8 tf "j h v > ^ )V f - y 7° t ÿ u a y \£ a . — ÿ ~ü"Ÿ o

Contextual Info: . February 1993 54AC/74AC109 • 54 ACT/74 ACT 109 Dual JK Positive Edge-Triggered Flip-Flop General Description The ’A C /’ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock

Contextual Info: T O SH IB A _ T C 74A C 14P/F/FN/FT TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC74AC14P, TC74AC14F, TC74AC14FN, TC74AC14FT Note The JEDEC SOP (FN) is not available in Japan HEX SCHMITT INVERTER

schaltungen

Abstract: 74AC EB209 SN74HC SN74HC00 SN74HC541 SN74HCT541 cmosschaltungen
Contextual Info: EB209 Spannungsbegrenzer EB209 BUS-HALTESCHALTUNG SN74ACT107x Verfasser: Eilhard Haseloff Datum: 17.07.1992 Rev.: * 1 Applikationslabor EB209 Spannungsbegrenzer Beim Entwurf von Systemen, die mit CMOS-Schaltungen aufgebaut werden, muß der Entwickler ein besonderes Augenmerk auf den Betriebsfall

Contextual Info: 74AXP1G58 Low-power configurable multiple function gate Rev. 2 — 24 July 2014 Product data sheet 1. General description The 74AXP1G58 is a configurable multiple function gate with Schmitt-trigger inputs. The device can be configured as any of the following logic functions AND, OR, NAND, NOR,

Contextual Info: 74AXP1G58 Low-power configurable multiple function gate Rev. 1 — 25 June 2013 Preliminary data sheet 1. General description The 74AXP1G58 is a configurable multiple function gate with Schmitt-trigger inputs. The device can be configured as any of the following logic functions AND, OR, NAND, NOR,

Contextual Info: 1SS309 T O SH IB A 1 SS309 TOSHIBA DIODE SILICON EPITAXIAL PLANAR TYPE Unit in mm ULTRA HIGH SPEED SWITCHING APPLICATIONS. + 0.2 2 .8 - 0 .3 • • • • Small Package Low Forward Voltage Fast Reverse Recovery Time Small Total Capacitance + 0.2 : SC-74A

S-808b

Abstract: S808B
Contextual Info: M ITSUBISHI ASTTLs M 74A S808B P HEX 2-IN PUT AND DRIVER DESCRIPTION The M 74A S 808B P is a sem iconductor integrated circuit PIN CONFIGURATION TOP VIEW — w — consisting of six 2-input positive-logic A N D buffer gates, usable as n egative-log ic OR buffer gates.

PD16337

Contextual Info: DATA SHEET NEC HYBRID INTEGRATED CIRCUIT MC-9400A 320 240 -BIT AC- PDP DRIVER MODULE DESCRIPTION T he M C -9 400 A is a PDP d rive r m odule th a t in co rp o ra te s five 6 4 -b it high bre akd ow n vo lta g e o u tp u t (150 V, 40 mA) C M O S d rive r ICs. It su p p o rts 320 o u tp u ts in the case of 4 -b it parallel input, and 240 ou tp u ts in the case of 3 -b it parallel

Contextual Info: MITSUBISHI ASTTLs M74AS832BP HEX 2-IN PU T OR DRIVER DESCRIPTION The M 74A S 832B P is a sem iconductor integrated circuit PIN CONFIGURATION TOP VIEW consisting of six 2-input positive-logic OR buffer gates, usable as negative-log ic A N D buffer gates.

Contextual Info: MITSUBISHI ASTTLs M74AS21P i DUAL 4 -INPUT POSITIVE AND GATE DESCRIPTION T he PIN CONFIGURATION TOP VIEW M 74A S 21P is a sem iconductor integrated circuit consisting of two 4-inp ut positive-logic A N D gates, us­ ab le as n egative-log ic OR gates. FEATURES

Contextual Info: M ITSUBISHI A S T T L s M 74A S00P QUADRUPLE 2 -INPUT POSITIVE NAND GATE DESCRIPTION PIN CONFIGURATION TOP VIEW Th e M 74A S 00P is a sem iconductor integrated circuit consisting of four 2-input positive-logic N A N D gates, us­ ab le as negative-log ic N O R gates.

Contextual Info: MITSUBISHI ASTTLs M 74AS1034AP .MV"4 HEX DRIVER DESCRIPTION PIN CONFIGURATION TOP VIEW The M 7 4A S 1 034 A P is a sem iconductor integrated circuit consisting of six non-inverting drivers. FEATURES IN P U T • High fan-out ( l 0 L= 48mA, Io h ^ - 48m A )

Contextual Info: 74AC11204 HEX INVERTER/CLOCK DRIVER D3427, O C TO BER 1989 DW OR N PACKAGE Low -Skew Propagation Delay TOP V IE W S pecifications for C lock Driver A pplications 1Y f Flow -Through A rchitecture O ptim izes PCB Layout • 19 ] 2A 3Y [ 3 16 ] 3A [ 4 E P IC '“ (E nhanced-P erform ance Im planted

1804P

Contextual Info: MITSUBISHI ASTTLs M 74AS804BP HEX 2-IN PU T NANO DRIVER DESCRIPTION The M 74A S 804B P is a sem iconductor integrated circuit consisting of six 2-input positive-logic NAND PIN CONFIGURATION TOP VIEW — buffer gates, usable as negative-log ic N O R buffer gates.

Contextual Info: MITSUBISHI -CDGTL L O GI C! b S l4ciñ27 0 D 1 S 2 5 7 b MITSUBISHI ASTTLs & M74AS832BP 7 -V 3 -ÏS HEX 2-IN PU T OR DRIVER 6249827 MITSUBISHI CD G T L LOGIC DESCRIPTION Th e M 74A S 832B P is a sem iconductor integrated circuit 91D D PIN CONFIGURATION TOP VIEW)

s32p

Abstract: 2p m 1y
Contextual Info: MITSUBISHI ASTTLs M 74A S 32P QUADRUPLE 2-IN PU T POSITIVE OR GATE DESCRIPTION PIN CONFIGURATION TOP VIEW The M 7 4A S 3 2P is a sem iconductor integrated circuit consisting of four 2-input positive-logic OR gates, us­ ab le as n egative-log ic A N D gates.

Contextual Info: Ha National Æ M Semiconductor 54ACT/74ACT112 Dual JK Negative Edge-Triggered Flip-Flop General Description The 'ACT 112 contains two independent, high-speed JK flipflops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Trig­

TMP87CH74AF

Abstract: TLCS-870 TMP87CM74AF TMP87PM74F 87CH74
Contextual Info: TOSHIBA TMP87CH74A/M74A CMOS 8-Bit M icrocontroller TMP87CH74AF, TMP87CM74AF The 87CH74A/CM74A are the high speed and high perform ance 8-bit single chip microcomputers. These MCU contain 8-bit A/D conversion inputs and a VFT Vacuum Fluorescent Tube driver on a chip.

Contextual Info: 74AC11204 HEX INVERTER/CLOCK DRIVER D3427, O C TO B ER 1989 DW OR N PACKAGE Low-Skew Propagation Delay Specifications for Clock Driver Applications TOP VIEW 1Y[ 1 2Y [ 2 3Y [ 3 Flow-Through Architecture Optimizes PCB Layout * * * Package Options Include Plastic “Small

Contextual Info: M ITS U B IS H I iDGTL L O G I C } "11 »e | LSM'ifla? 9 1 D 12 1 7 6 D , DDiai7b t f ” MITSUBISHI ASTTLs M 74A S 02P QUADRUPLE 2-IN PU T POSITIVE NOR GATE DESCRIPTION PIN CONFIGURATION TOP VIEW T h e M 7 4A S 0 2P is a sem iconductor integrated circuit

cd74ac00

Abstract: 74AC series
Contextual Info: Technical Data CD54/74AC00 CD54/74ACT00 1* 1 1. 2 • 4 2A-5 28-3A-3. 10 y- 3 -» Quad 2-Input NAND Gate « jy - =1 4A 12 4B ” = 1 yy- 8 - 31 Type Features: ■ Typical propagation delay AC00 : 3.2ns @Vcc = 5 V, 7a = 25° C, C L = 50 pF 11 - 4Y