12 line ccd scanner
Abstract: toshiba 2400 dpi cis sensor nec CCD LINEAR IMAGE SENSOR flatbed scanner controller CCD LINEAR SENSOR 512 linear ccd ST L6219 application note block diagram of paper scanner CCD linear 10 ccd sony
Text: Ru.4 Xu062 f Genesys Logic, Inc. GL848 High Speed USB 2.0 2-in-1 Scanner Controller With Fast ADF & Bus Power Datasheet Revision 1.00 December 17, 2007 GL848 High Speed USB2.0 2-in-1 Scanner Controller With Fast ADF Copyright: Copyright 2006 Genesys Logic Incorporated. All rights reserved. No part of the materials may be
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Xu062
GL848
GL848
QFP-128L
12 line ccd scanner
toshiba 2400 dpi cis sensor
nec CCD LINEAR IMAGE SENSOR
flatbed scanner controller
CCD LINEAR SENSOR 512
linear ccd
ST L6219 application note
block diagram of paper scanner
CCD linear
10 ccd sony
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EXS00A-CG02811
Abstract: rm - 64k DSA00811285.txt capacitor y3p EXS00A-CG
Text: CDCM6208 www.ti.com SCAS931 – MAY 2012 2:8 CLOCK GENERATOR, JITTER CLEANER WITH FRACTIONAL DIVIDERS Check for Samples: CDCM6208 FEATURES 1 • Superior Performance with Low Power: – Low Noise Synthesizer 265 fs-rms Typical Jitter or Low Noise Jitter Cleaner (1.6 psrms Typical Jitter)
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CDCM6208
SCAS931
EXS00A-CG02811
rm - 64k
DSA00811285.txt
capacitor y3p
EXS00A-CG
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Untitled
Abstract: No abstract text available
Text: Ordering number : EN*A2253 LV25500PQA Advance Information Bi-CMOS LSI http://onsemi.com FM Multiplex Broadcasting Receive Tuner Overview LV25500PLF is in-vehicle FM multiplex broadcasting receive only tuner IC that makes FM tuner, PLL, and the RDS demodulator single-chip.
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A2253
LV25500PQA
LV25500PLF
A2253-13/13
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LTC3544B
Abstract: LTC3544 SW100 Wurth 47uH LTC3562
Text: LTC3544B Quad Synchronous Step-Down Regulator: 2.25MHz, 300mA, 200mA, 200mA, 100mA Features Description High Efficiency: Up to 95% • Four Independent Regulators Provide Up to 300mA, 200mA, 200mA and 100mA Output Current ■ 2.25V to 5.5V Input Voltage Range
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LTC3544B
25MHz,
300mA,
200mA,
100mA
200mA
100mA
LTC3544B
LTC3544
SW100
Wurth 47uH
LTC3562
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MA17
Abstract: MA18 MX98728EC Macronix marking GMAC
Text: MX98728EC 1.0 Features GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION • 1.6KB TX FIFO to support maximum network throughput in the full duplex mode • 16/8 bits SRAM interface of the packet buffer supporting burst DMA for on-chip FIFOs
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MX98728EC
C9930
TA777001
38BAX
MA17
MA18
MX98728EC
Macronix marking
GMAC
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Untitled
Abstract: No abstract text available
Text: RTL8305SB -Ver. D SINGLE-CHIP 5-PORT 10/100MBPS SWITCH CONTROLLER WITH DUAL MII INTERFACES DATASHEET Rev. 1.2 10 June 2003 Track ID: JATR-1076-21 RTL8305SB-Ver. D Datasheet COPYRIGHT 2003 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted,
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RTL8305SB
10/100MBPS
JATR-1076-21
RTL8305SB-Ver.
JATR-1076-21
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RTL8305
Abstract: No abstract text available
Text: RTL8305SB SINGLE-CHIP 5-PORT 10/100MBPS SWITCH CONTROLLER DATASHEET Rev. 1.4 02 April 2004 Track ID: JATR-1076-21 RTL8305SB Datasheet COPYRIGHT 2004 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
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RTL8305SB
10/100MBPS
JATR-1076-21
RTL8305
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Untitled
Abstract: No abstract text available
Text: RTL8305SB -Ver. D SINGLE-CHIP 5-PORT 10/100MBPS SWITCH CONTROLLER WITH DUAL MII INTERFACES DATASHEET Rev. 1.3 05 April 2004 Track ID: JATR-1076-21 RTL8305SB-Ver. D Datasheet COPYRIGHT 2004 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
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RTL8305SB
10/100MBPS
JATR-1076-21
RTL8305SB-Ver.
JATR-1076-21
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TM070
Abstract: p5md AD10 AD11 AD12 MN10200 MN102H460B tm10b BR17
Text: M IC R O C O M P U T E R M N 102H00 MN102H460B LSI 説明書 Pub.No.22346-011 PanaXSeriesは松下電器産業株式会社の商標です。 その他記載された会社名及びロゴ、製品名などは該当する各社の商標または登録商標です。
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102H00
MN102H460B
00FE80'
00FEFF'
MN10200
MN10200
TM070
p5md
AD10
AD11
AD12
MN102H460B
tm10b
BR17
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S1ZB60
Abstract: No abstract text available
Text: IA3222/3223-EVB IA3222/3223 D E MO B OA RD AND C P L D I N T E R P O S E R U S E R ’ S G UIDE Description Features The IA3222/3223 Demo Board is a typical application circuit that exhibits all the features of the IA3222/3223 chipset. The chipset can be programmed by software to
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IA3222/3223-EVB
IA3222/3223
IA3222/3223
S1ZB60
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f4ha
Abstract: MX08 LM4560 ymf262 opl3 SNAS029
Text: LM4560 LM4560 Advanced PCI Audio Accelerator Literature Number: SNAS029 LM4560 Advanced PCI Audio Accelerator General Description LM4560 is an advanced PCI audio accelerator providing full legacy compatibility, wavetable synthesis, DirectMusic, DirectSound, and DirectSound3D on a single chip for the highperformance, cost-sensitive consumer market. It supports
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LM4560
LM4560
SNAS029
64-voice
f4ha
MX08
ymf262
opl3
SNAS029
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LTC3544
Abstract: VFB-100 SW200A SW200B SW100 TPC744029 SW100B LTC3544B
Text: LTC3544 Quad Synchronous Step-Down Regulator: 2.25MHz, 300mA, 200mA, 200mA, 100mA FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High Efficiency: Up to 95% Four Independent Regulators Provide Up to 300mA, 200mA, 200mA and 100mA Output Current 2.25V to 5.5V Input Voltage Range
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LTC3544
25MHz,
300mA,
200mA,
100mA
200mA
100mA
LTC3544
VFB-100
SW200A
SW200B
SW100
TPC744029
SW100B
LTC3544B
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marking gb0
Abstract: SPREAD-SPECTRUM SYSTEM
Text: ICS1532 110 MHZ TRIPLE 8-BIT ADC WITH CLOCK GENERATOR General Description Features The ICS1532 is a high-performance, cost-effective, 3-channel, 8-bit analog-to-digital converter with an integrated line-locked clock generator. They are part of a family of chips for high-resolution video
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ICS1532
ICS1532
marking gb0
SPREAD-SPECTRUM SYSTEM
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63D12
Abstract: No abstract text available
Text: Advanced Information NPC401QFA-100 SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION 1.0 Features • 32 bits general purpose asynchronous bus architecture up to 33Mhz for easy system application • Single chip solution integrating 10/100 TP transceiver to reduce overall cost
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NPC401QFA-100
33Mhz
NPC401QFA-100-01
63D12
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Fast Ethernet
Abstract: 88E3018 88e3015 88e3018nnc1 Marvell PHY register map 88E3018 QFN-64 Marvell PHY 88E3018 layout 88E301 marvell rgmii layout CTRL25 BJT MARVELL 88
Text: 88E3015/88E3018 Integrated 10/100 Fast Ethernet Transceiver Doc. No. MV-S103657-00, Rev. D January 4, 2008 Document Classification: Proprietary Information Marvell. Moving Forward Faster 88E3015/88E3018 Integrated 10/100 Fast Ethernet Transceiver Document Status
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88E3015/88E3018
MV-S103657-00,
Fast Ethernet
88E3018
88e3015
88e3018nnc1
Marvell PHY register map
88E3018 QFN-64
Marvell PHY 88E3018 layout
88E301
marvell rgmii layout CTRL25 BJT
MARVELL 88
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IP101A
Abstract: IC Plus MLT 22 713 100BASET4
Text: IP101A LF Data Sheet Single port 10/100 Fast Ethernet Transceiver Features General Description 10/100Mbps TX Full-duplex or half-duplex Supports Auto MDI/MDIX function Fully compliant with IEEE 802.3/802.3u Supports IEEE 802.3u auto-negotiation Supports MII / RMII / SNI interface
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IP101A
10/100Mbps
25MHz
50MHz
LF-DS-R17
IC Plus
MLT 22 713
100BASET4
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Automatic Gain Control AGC Algorithm Users
Abstract: AIC28 TSC2100 AIC32 AIC26 TLV320AIC26 TLV320AIC33 TSC2101 "saturation flag"
Text: Application Report SLAA260 – September 2005 The Built-In AGC Function in TSC2100/01 and TLV320AIC26/28/32/33 Devices Wendy Fang and Nitesh Kekre . DAP Group ABSTRACT
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SLAA260
TSC2100/01
TLV320AIC26/28/32/33
TLV320AIC26/28/32/33
Automatic Gain Control AGC Algorithm Users
AIC28
TSC2100
AIC32
AIC26
TLV320AIC26
TLV320AIC33
TSC2101
"saturation flag"
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h1632
Abstract: Macronix marking ds130 diode MAR7 MA17 MA18 MX98728EC Long teim timer 4D70 LTPS
Text: MX98728EC 1.0 Features GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION • 1.6KB TX FIFO to support maximum network throughput in the full duplex mode • 16/8 bits SRAM interface of the packet buffer supporting burst DMA for on-chip FIFOs
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MX98728EC
C9930
TA777001
38BAX
h1632
Macronix marking
ds130 diode
MAR7
MA17
MA18
MX98728EC
Long teim timer
4D70
LTPS
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80C51
Abstract: SAA4974 frame up-conversion overlay 1998
Text: APPLICATION NOTE I²C-bus Register Specification for the SAA4974 V1.0 AN97042 Philips Semiconductors I²C-bus Register Specification for the SAA4974 V1.0 Application Note REVISION HISTORY Version Remarks 0.1 DRAFT; 18.06.97 1.0 First Release; 30.07.97 Purchase of Philips I2C components conveys a
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SAA4974
AN97042
80C51
SAA4974
frame up-conversion overlay 1998
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CY7C955
Abstract: No abstract text available
Text: CY7C955 PRELIMINARY AX ATM-SONET/SDH Transceiver — Line Far End Receive Failure Features • WAN and LAN ATM physical layer device • Provides complete physical layer transport of ATM cells at — STS−3c/ STM−1 rate of 155.52 MHz — STS−1 rate of 51.84M Hz
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CY7C955
CY7C955
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ITT 90 38 TCA 700 Y
Abstract: ITT G 91 38 TCA 700 y ITT TCA 700 Y REG-52H Delta Electronics dps -300HB A Delta Electronics dps -350MB A reg51 Delta Electronics dps Delta Electronics DPS 350MB-3a Delta Electronics dps 500
Text: PRESS CY7C955 PRELIMINARY AX ATM-SONET/SDH Transceiver Features — Line Far End Receive Failure — Line Alarm Indication Signal * WAN and LAN ATM physical layer device * Provides com plete physical layer transport of ATM cells at: — B1 Parity Error
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CY7C955
GR-253
ITT 90 38 TCA 700 Y
ITT G 91 38 TCA 700 y
ITT TCA 700 Y
REG-52H
Delta Electronics dps -300HB A
Delta Electronics dps -350MB A
reg51
Delta Electronics dps
Delta Electronics DPS 350MB-3a
Delta Electronics dps 500
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h145
Abstract: No abstract text available
Text: AX ATM-SONET/SDH Transceiver — Line Far End Receive Failure Featu res * WAN and LAN ATM physical layer device * P rovides co m p le te physical layer tr a n s p o rt o f ATM cells at — S T S -3 c / STM-1 rate of 155.52 MHz — Line Alarm Indication Signal
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GR-253,
h145
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Untitled
Abstract: No abstract text available
Text: / T 7 S C S -T H O M S O N *7 M , « IM ilL Ë O T IM O S T V 0 1 1 6 PAL/NTSC DIGITAL ENCODER • BOTH 625 & 525 LINES MULTIPLEXED 8 BIT DIGITAL INPUT ACCORDING TO CCIR 601 -2 AND REC 656 ■ NTSC M, PALB, D, G, H, I, PAL N ARGEN TINA PROGRAMMABLE OUTPUT
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75MHz
27MHz
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LM4560
Abstract: No abstract text available
Text: Semiconductor LM4560 Advanced PCI Audio Accelerator General Description The LM4560 integrates a 64-voice wave table engine with per voice effect processing capability. It supports the upcom ing Microsoft DirectMusic API and is fully compatible with DLS Level 1 downloadable samples specification. The
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LM4560
64-voice
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