DW0045-28
Abstract: MF-622DF-T12-XXX S3017 S3018 STM-16 STS-48 T12xx
Text: DEVICE SPECIFICATION SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER BiCMOS PECL CLOCK SONET/SDH/ATM OC-12GENERATOR TRANSMITTER TRANSMITTER AND AND RECEIVER RECEIVER GENERAL DESCRIPTION FEATURES • Complies with ANSI, Bellcore, and ITU-T specifications • On-chip high-frequency PLL for clock
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OC-12
OC-12/STM-4)
S3017/S3018
DW0045-28
MF-622DF-T12-XXX
S3017
S3018
STM-16
STS-48
T12xx
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S3021
Abstract: No abstract text available
Text: DEVICE SPECIFICATION ATM 622 MBIT/S TRANSMITTER AND RECEIVER BiCMOS PECL CLOCK SONET/SDH/ATM ATM 622 MBIT/S TRANSMITTER OC-12GENERATOR TRANSMITTER AND RECEIVER AND RECEIVER GENERAL DESCRIPTION FEATURES • Complies with ANSI, Bellcore, and ITU-T specifications
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OC-12
S3020/S3021
S3020/S3021
OC-12/STM-4)
S3021
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SDM4123-XC
Abstract: 156DS
Text: DEVICE SPECIFICATION S3011/S3012 S3011/S3012 SONET/SDH/ATM OC-3 TRANSMITTER AND RECEIVER SONET/SDH/ATM OC-3 GENERATOR TRANSMITTER AND RECEIVER BiCMOS PECL CLOCK GENERAL DESCRIPTION FEATURES • Complies with ANSI, Bellcore, and ITU-T specifications • On-chip high-frequency PLL for clock
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S3011/S3012
S3011/S3012
SDM4123-XC
156DS
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Astrotec
Abstract: coded mark inversion S3005 S3006 T12xx
Text: DEVICE SPECIFICATION SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER GENERAL DESCRIPTION FEATURES • Complies with ANSI, Bellcore, and ITU-T specifications • On-chip high-frequency PLL for clock generation and clock recovery
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OC-3/12
OC-12)
OC-3/12)
Astrotec
coded mark inversion
S3005
S3006
T12xx
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volgers
Abstract: 74HC4046A 74HC-HCT4046A AN12 CS61574 CS61574A CS61575 AN12REV2 Stratum 3 digital PLL Phase-locked loop circuits
Text: AN12 Application Note AT&T 62411 Design Considerations Jitter and Synchronization By Bob Bridge SYNCHRONIZATION OF DIGITAL NETWORKS INTRODUCTION This application note outlines the technical requirements which must be considered when designing a system to meet the AT&T 62411 synchronization and jitter requirements. The first
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74HC4046A
AN12REV2
74HC/HCT4046A
74HC/HCTR7046A
CD54/74HC/HCT
volgers
74HC4046A
74HC-HCT4046A
AN12
CS61574
CS61574A
CS61575
AN12REV2
Stratum 3 digital PLL
Phase-locked loop circuits
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syn 7580
Abstract: BT8510EPJC PCM30 CODEC HCT4046A 74hc4040 model simulator slip ring TS16 4046 cmos SR09 G705
Text: Bt8510 E1 Controller With Physical Line Interface The Bt8510 is a highly integrated E1/CEPT transceiver that performs framing, control, and monitoring of E1 and Integrated Services Digital Network ISDN Primary Rate signals operating at 2.048 Mb/s. The Bt8510 is compatible with popular E1/CEPT framing standards such as ITU-T Recommendations G.704 (PCM-30), G.732 (CAS), and G.706 (CRC4). The two-frame Pulse Code Modulation (PCM) slip buffer adapts the receive clock and
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Bt8510
Bt8510
PCM-30)
768MHz
L8510001
syn 7580
BT8510EPJC
PCM30 CODEC
HCT4046A
74hc4040 model simulator
slip ring
TS16
4046 cmos
SR09
G705
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amcc CDR
Abstract: SDH ADM TA-NWT-000253 OC-24 S1201 S3035 STM-16 STS-48
Text: DEVICE SPECIFICATION SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR BiCMOS LVPECL OC-12 CLOCKTRANSMITTER GENERATOR SONET/SDH/ATM OC-3/12 TRANSCEIVERAND W/CDR RECEIVER FEATURES GENERAL DESCRIPTION • Complies with Bellcore and ITU-T specifications • On-chip high-frequency PLLs for clock
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OC-3/12
OC-12
OC-12)
amcc CDR
SDH ADM
TA-NWT-000253
OC-24
S1201
S3035
STM-16
STS-48
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OC-24
Abstract: S3019 STM-16 STS-48
Text: DEVICE SPECIFICATION SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR BiCMOS LVPECL OC-12 CLOCKTRANSMITTER GENERATOR SONET/SDH/ATM OC-3/12 TRANSCEIVERAND W/CDR RECEIVER FEATURES GENERAL DESCRIPTION • Complies with Bellcore and ITU-T specifications • On-chip high-frequency PLLs for clock
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OC-3/12
OC-12
OC-12)
D260/R463
OC-24
S3019
STM-16
STS-48
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OC-24
Abstract: S3019 STM-16 STS-48
Text: DEVICE SPECIFICATION SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR BiCMOS LVPECL OC-12 CLOCKTRANSMITTER GENERATOR SONET/SDH/ATM OC-3/12 TRANSCEIVERAND W/CDR RECEIVER FEATURES GENERAL DESCRIPTION • Complies with Bellcore and ITU-T specifications • On-chip high-frequency PLLs for clock
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OC-3/12
OC-12
OC-12)
OC-24
S3019
STM-16
STS-48
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Untitled
Abstract: No abstract text available
Text: DEVICE SPECIFICATION SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR BiCMOS LVPECL OC-12 CLOCKTRANSMITTER GENERATOR SONET/SDH/ATM OC-3/12 TRANSCEIVERAND W/CDR RECEIVER FEATURES GENERAL DESCRIPTION • Complies with ANSI, Bellcore, and ITU-T specifications • On-chip high-frequency PLLs for clock
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OC-3/12
OC-12
S3019
S3019
OC-12)
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S3035
Abstract: OC-24 S1201 STM-16 STS-48
Text: DEVICE SPECIFICATION SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR BiCMOS LVPECL OC-12 CLOCKTRANSMITTER GENERATOR SONET/SDH/ATM OC-3/12 TRANSCEIVERAND W/CDR RECEIVER FEATURES GENERAL DESCRIPTION • Complies with Bellcore and ITU-T specifications • On-chip high-frequency PLLs for clock
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OC-3/12
OC-12
OC-12)
S3035
OC-24
S1201
STM-16
STS-48
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Untitled
Abstract: No abstract text available
Text: f i | Product Description Features and Modes of Operation This specification describes the Bt8510 E l (often called CEPT or DS1A frame synchronization, signal generation, and recovery circuit for application in digital terminal interfaces operating at 2.048 Mb/s. Applications for this device include
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Bt8510
HV53-200
768MHz
Bt8510
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68HCll
Abstract: PE-64931 CR003 BT8510EPJC 68HC11 TS16 0x80-0x9F sr002
Text: f i| Product Description Features and Modes of Operation This specification describes the Bt8510 El (often called CEPT or DS1A) frame synchronization, signal generation, and recovery circuit for application in digital terminal interfaces operating at 2.048 Mb/s. Applications for this device include
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Bt8510
HV53-200
768MHz
Bt8510_
68HCll
PE-64931
CR003
BT8510EPJC
68HC11
TS16
0x80-0x9F
sr002
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G705
Abstract: No abstract text available
Text: Product Description Features and Modes of Operation This specification describes the Bt8510 El often called CEPT or DS1A frame synchronization, signal generation, and recovery circuit for application in digital terminal interfaces operating at 2.048 Mb/s. Applications for this device include
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Bt8510
HV53-200
768MHz
Bt8510
L8510001
G705
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BT8300
Abstract: No abstract text available
Text: T -l ESF/CLEAR-CHANNEL FRAMER Bt8300 1 .0 INTRODUCTION This specification describes a dual T-l frame-synchronization and signal generation and recovery circuit for application in digital terminals that are synchronized to a local or recovered source of frame clock at 8 kHz. These
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Bt8300
IS30143
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fiber T27 TIMER
Abstract: No abstract text available
Text: RCC521 RCC521 STS-3/STM-1 Synchronizer and Framer General Description Features The RCC521 STS-3/STM-1 Synchronizer and Framer provides all the frame recognition and synchronization functions required of a SONET/SDH line interface at the 155.52 Mb/s data rate. On-chip phase-locked loops
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RCC521
RCC521
TR-NWT000253.
65-6200M
fiber T27 TIMER
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photonic crystal fiber
Abstract: SDM4123-XC
Text: DEVICE SPECIFICATION S O N E T /S D H /A TM OC-3 TR A N S M ITTE R AN D RECEIVER FEATURES • Complies with ANSI, Bellcore, and ITU-T specifications • On-chip high-frequency PLL for clock generation and clock recovery • Supports 155.52 Mbit/s OC-3 • Reference frequency of 19.44 MHz
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S3011/S3012
S3011/S3012
photonic crystal fiber
SDM4123-XC
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fiber T27 TIMER
Abstract: No abstract text available
Text: RCC521 STS-3/STM-1 Synchronizer and Framer General Description Features The RCC521 STS-3/STM-1 Synchronizer and Framer provides all the frame recognition and synchronization functions required of a SONET/SDH line interface at the 155.52 Mb/s data rate. On-chip phase-locked loops
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RCC521
TR-NWT000253.
65-6203M
RCC521
fiber T27 TIMER
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P1N5
Abstract: T12xx
Text: DEVICE SPECIFICATION S O N E T/SD H /ATM OC-12 TR AN SM ITTER AN D RECEIVER FEATURES • Complies with ANSI, Bellcore, and ITU-T specifications • On-chip high-frequency PLL for clock generation and clock recovery • Supports 622.08 Mbit/s OC-12/STM-4
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OC-12
S3017/S3018
OC-12/STM-4)
S3017/S3018
SONETOC-12
3017/S
w/DW0045-28
w/DW0045-29
P1N5
T12xx
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T12xx
Abstract: No abstract text available
Text: DEVICE SPECIFICATION ATM 622 M BIT/S TR AN SM ITTER AN D RECEIVER FEATURES Complies with ANSI, Bellcore, and ITU-T specifications On-chip high-frequency PLL for clock generation and clock recovery Supports 622.08 Mbit/s OC-12/STM-4 Reference frequencies of 19.44 and
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S3020/S3021
OC-12/STM-4)
S3020/S3021
S3020
CA92121
T12xx
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AM 770 DENSITY TRANSMITTER
Abstract: T12xx 8829C
Text: DEVICE SPECIFICATION SO N E T /SD H /AT M OC-12 T R AN SM ITTER AND RECEIVER FEATURES • Complies with ANSI, Bellcore, and ITU-T specifications • On-chip high-frequency PLL for clock generation and clock recovery • Supports 622.08 Mbit/s OC-12/STM-4
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OC-12
S3017/S3018
OC-12/STM-4)
S3017/S3018
SONETOC-12
w/DW0045-28
w/DW0045-29
AM 770 DENSITY TRANSMITTER
T12xx
8829C
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27852
Abstract: 46421
Text: KiEP f ? 1982 PRELIMINARY DEVICE SPECIFICATION S3008/S3009 E4 Transmitter and Receiver GENERAL DESCRIPTION FEATURES • Complies with CCITT specifications • On-chip high-frequency PLL for clock generation and clock recovery • Supports 139.264 Mbit/s E4 transmission rate
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S3008/S3009
A7D4510-0692
27852
46421
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Untitled
Abstract: No abstract text available
Text: DEVICE SPECIFICATION SONET/SDH/ATM OC-12 TRANSMUTER AND RECEIVER GENERAL DESCRIPTION FEATURES • Complies with ANSI, Bellcore, and ITU-T specifications • On-chip high-frequency PLL for clock generation and clock recovery • Supports 622.08 Mbit/s OC-12/STM-4
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OC-12
S3017/S3018
OC-12/STM-4)
S3017/S3018
SONETOC-12
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S3005/S3006
Abstract: T12xx
Text: DEVICE SPECIFICATION SO NET/SDH OC -3/12 T R AN SM ITTER AND RECEIVER GENERAL DESCRIPTION FEATURES • Complies with ANSI, Bellcore, and ITU-T specifications • On-chip high-frequency PLL for clock generation and clock recovery • Supports 139.264 Mbit/s E4 , 155.52 Mbit/s
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S3005/S3006
OC-12)
OC-3/12)
S3005/S300b
S3005/S3006
T12xx
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