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STM32F10E-EVAL

Abstract: dmx512 receiver ic 7490 pin diagram DMX RECEIVER IC DMX512 RECEIVER IC DMx512 ic internal diagram of 7490 IC UM1004 dmx512 stm32 dmx512
Contextual Info: UM1004 User manual DMX 512 based LED lighting solution Introduction This document describes how to use the demonstration firmware for the DMX512 communication protocol for transmitter, receiver, and standalone mode. The USART universal synchronous asynchronous receiver transmitter module of the STM32F103C6

DMX RECEIVER

Abstract: dmx512 receiver UM0791 STM32 firmware library dmx 512 receiver DMX 512 dmx-512 STM32F103Zx stm32 dmx512 dmx512 arm STM32 firmware library
Contextual Info: UM0791 User manual Demonstration firmware for the DMX-512 communication protocol receiver based on the STM32F103Zx Introduction This document describes how to use the demonstration firmware for the DMX-512 communication protocol receiver. The USART universal synchronous asynchronous

HT6547E-2

Contextual Info: HDLTEK r r HT82K28A Win98 Keyboard Encoder Prelim inary Features • Designed for Windows 95/98/NT • Supports 3 Windows 95 Keys • Supports Power, Sleep and Wake-up Win­ dows 98 ACPI functions • Supports Japanese, Korean and Portuguese • Supports Japanese DOS/V 106-key

ATIC 107

Abstract: ATIC 64 C1 ATIC 59 C1 atic 106 ATIC 59 ATIC 39 b4 ATIC 112 6547E HT6547E ATIC 43
Contextual Info: HOLTEK r r HT6547E Win95 Keyboard Encoder With Japanese Features • S up ports 3 W indow s Keys • S up ports Ja p a n e se DOS/V 106-key keyboard • S up ports code set 1, for PS/2 m odel 30 keyboard • S up ports code set 2, for PC/AT, PS/2 m odel 50,60 keyboards

ATIC 39 b4

Abstract: SC014 ATIC 09 b4
Contextual Info: HOLTEK r r HT6547D Win95 Keyboard Encoder with Japanese Features • Supports 3 Windows Keys • Supports Japanese Keyboard • Supports code set 1, for PS/2 model 30 key­ board • Supports code set 2, for PC/AT, PS/2 model 50,60 keyboards • LC oscillator

RK31

Contextual Info: HOLTEK HT9305xR 5-Memory with ABR Tone/Pulse Dialer Features Patent Number: 64097, 86474, 112678, 113235 R.O.C. 5424740 (U.Sj V.) U niversal specification O perating voltage: 2.0V~5.5V Low standby current Low memory retention current: 0.1|iA (Typ.) Tone/pulse switchable

tmp8251ap

Abstract: tmp8251 82C51 tmp8251a 82C51A USART 8251 pin diagram 8251A intel 8251 USART control word format 8251A intel 8251
Contextual Info: TOSHIBA TMP82C51A TMP82C51AP-2 /TMP82C51AP-10 TMP82C51 AM-2/TMP82C51 AM-10 PRO GRAM M ABLE COMMUNICATION INTERFACE 1. GENERAL DESCRIPTION The TM P82C51A is the in d u stry stan d ard U niversal Synchronous/A synchronous R eceiver/T ransm itter USART th a t is fabricated using C-MOS silicon g ate technology.

lls 9300

Abstract: amprobe am
Contextual Info: Part No. 79-0001-10 6/95 REV. A ▲ «=• ^= ^ AmL~a "m1p r o ¥ e DIVISION OF CORE INDUSTRIES INC. UYNBftOOK NEW YORK 11583 «30 MERRICK ROAD. P.O. BOX 328 AREA CQOE 516 503-5000« FAX (61«) 59^5602 Made in USA US Patent Nos. 4,491,785; 4,642,556;

Contextual Info: XE2400MNP 2400 bps Error Correcting Component Modem Description Features Small Size - 2.75" x 1.38" x 0.5" FCC Part 68 Registered Full 2400/1200/300 bps Transmission Capability MNP transfer protocol through Gass 5 CCITT V.22 bis, V.22/V.21 and Bell 212A/103 Compatible

P8251A

Abstract: P82C51A tmp8251 82C51A P8251
Contextual Info: T O S H IB A TM P82C51A TMP82C51AP-2 /TMP82C51AP-10 TMP82C51 AM-2/TMP82C51 AM-10 PROGRAM M ABLE COMMUNICATION INTERFACE 1. GENERAL DESCRIPTION T he TM P82C51A is th e in d u stry sta n d a rd U n iv ersa l S ynchron o u s/A sy n ch ro n o u s R eceiver/T ransm itter USART th a t is fabricated u sin g C-MOS silicon g a te technology.

ATIC 39 b4

Abstract: ATIC 09 b4 ATIC 59 F9348 F9321 27EO
Contextual Info: HOLTEK r r HT6549A Win95 Keyboard Encoder with Japanese Features • Supports 3 Windows Keys • Supports Japanese DOS/V 106-key Keyboard • Supports code set 1, for PS/2 model 30 keyboard • Supports code set 2, for PC/AT, PS/2 model 50,60 keyboards • Supports code set 3, for PS/2 model

keypad Encoder IC 5x5 matrix

Abstract: keyboard CIRCUIT diagram
Contextual Info: HOLTEK H T Features • • • • • • • • • • HT9242A/B/AL/BL/CL/DL 12-Memory Tone/Pulse Dialer Patent Number: 86474, 113235 R.O.C. , 5424740(U.S.A.) U n iversal specification O perating voltage: 2.0V~5.5V Low stan dby current Low m emory retention current: O.ljiA (Typ.)

stm32 dmx512

Abstract: UM0792 DMA stm32 dmx STM32 firmware library rs485 stm32 dmx512 receiver STM32F103Zx DMX 512 DMX RECEIVER pin diagram of max 485
Contextual Info: UM0792 User manual Demonstration firmware for the DMX-512 communication protocol transmitter based on the STM32F103Zx Introduction This document describes how to use the demonstration firmware for the DMX-512 communication protocol transmitter. The USART universal synchronous asynchronous

Contextual Info: ASYNCHRONOUS COMMUNICATION ELEMENT KS82C50A FEATURES DESCRIPTION • Single Chip UART/BRG • DC to 10 MHz Operation DC to 625K Baud • Crystal or External Clock Input • On Chip Baud Rate Generator 1 to 65535 Divisor Generates 16x Clock • Prioritized Interrupt Mode

Z80 dart

Abstract: Z80A dart Z80B-DART z80 sio rs232 S9330 z80ADART Z80 40 pin Z8470 Z80BDART z8470aps
Contextual Info: Z 8470 Z80 DART D ual A synchronous R eceiver/T ransm itter Product Specification S e p te m b e r 1983 F ea tu res • Two in d e p e n d e n t fu ll-d u p le x c h a n n e ls with s e p a ra te m o d em co n tro ls. M odern statu s c an b e m o n ito re d .

HT9202F

Abstract: HT9202H HT9202G ht16xx 4x4 keyboard ht9202c HT9202A DIALER HT9202 4x4 matrix keypad block diagram
Contextual Info: HOLTEK H r HT9202A/B/C/D/F/G/H/L/S 1-Memory/2-Memory Tone/Pulse Dialer Faxback Doc. # 9007546 Features • • • • • • • • • • • • • • • • • U niversal specification O perating voltage: 2.0V-5.5V Low stand-by cu rren t Low mem ory retention current: 0. ljtA Typ.

HT16XX

Abstract: HT3810 HT9245 HT9245A HT9245AL HT9245B HT9245BL HT9245CL HT9245DL HT381XX
Contextual Info: HOLTEK r n r ^ Features • • • • • • • • • • HT9245A/B/AL/BL/CL/DL 15-Memory Tone/Pulse Dialer Patent Number: 86474,113235 R.O.C. , 5424740(U.S.A.) • • • • • • • • • • U niversal specification O perating voltage: 2.0V~5.5V

EL4453C

Contextual Info: Multiplier/Variable Gain Amplifiers Miti Sain 90 1 4 Quad Mult Full Scale Input V peak I reak 2V Signal Port (% ) Gain Port (% ) 0.35 0.2 Package Supply Current (mA) ±3 to ±16.5 15.4 ✓ 1 ¡M l': i& | 4 Quadrant E14450C Bandwidth @-3dB (MHz) 1 Supply Voltage

P3460

Contextual Info: M arch 1990 TP3460 ISDN R Interface USART General Description The TP 3460 is a U SART w hich, w hen co nn e cte d to a co n ­ trol p roce sso r running th e appropriate softw are w ith a c­ cess to an ISDN B-channel, enables a sta n d ard s com pliant

4x3 matrix keyboard

Abstract: UM9151-3 4x3 matrix keypad operation of 4x3 keypad UM9151 KEYPAD 4x3 Telephone Dialer Circuit 182 KEYPAD telephone 10PPS 4x3 keypad
Contextual Info: • « ■ « i w ■ UMC •■••• <PUMC Pulse Dialer Features Direct telephone line operation Redial w ith either # or ft key 4 x 3 matrix keyboard interface Dialer reset for line power breaks > 2 0 0 ms Supply voltage range of 2.0 to 5.5 volts 800 ms inter-digit pause

Contextual Info: ylV SC11008 Stand-Alone Modem Interface Controller SIERRA SEMICONDUCTOR □ □ C o m p le te A T c o m m a n d se t in fir m w a r e fo r in t e l l i g e n t m odem s □ 28-pin D IP o r PLC C package G E N E R A L DESCRIPTION T h e S C 1 1 0 0 8 M o d e m In te rfa c e

T9242AL

Abstract: 9242A
Contextual Info: HOLTEK r n r ^ Features • • • • • • • • • • HT9242A/B/A L/BL/CL/DL 12-Memory Tone/Pulse Dialer Patent Number: 86474,113235 R.O.C. , 5424740(U.S.A.) • • • • • • • • • • U n iv e rsa l specification O p e ra tin g voltage: 2.0V~5.5V

XR68C681

Contextual Info: Z * E X q R _ XR-88C681/68C681 CMOS Dual Channel UART DUART G EN ER AL DESCRIPTION Maximum Bit Rate: 1x Clock -1 Mb/Sec, 16x Clock - 125Kb/Sec Normal, Autoecho, Local Loopback, and Remote Loopback Modes Multi-Function 16-Bit Counter/Tim er Interrupt O utput with Eight Maskable Interrupting Cond.

M15F2G16128A

Contextual Info: ESMT M15F2G16128A DDR III SDRAM 16M x 16 Bit x 8 Banks DDR III SDRAM Feature z 1.5V ± 0.075V JEDEC Standard Power Supply z Output Driver Impedance Control z 8 Internal memory banks (BA0- BA2) z Differential bidirectional data strobe through ZQ pin z Differential clock input (CK, CK )