Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    RD 1H 107 M 08 11M PF Search Results

    RD 1H 107 M 08 11M PF Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    5962-9762201QEA Texas Instruments Quad LVDS Receiver 16-CDIP -55 to 125 Visit Texas Instruments Buy
    SN65LV1023ARHBR Texas Instruments 10:1 LVDS Serdes Transmitter 100 - 660Mbps 32-VQFN -40 to 85 Visit Texas Instruments Buy
    SN65LV1224BDBR Texas Instruments 1:10 LVDS Serdes Receiver 100 - 660Mbps 28-SSOP -40 to 85 Visit Texas Instruments Buy
    SN65LVCP22DR Texas Instruments 2x2 Crosspoint Switch : LVDS Outputs 16-SOIC -40 to 85 Visit Texas Instruments Buy
    SN65LVCP23PW Texas Instruments 2x2 Crosspoint Switch : LVPECL Outputs 16-TSSOP -40 to 85 Visit Texas Instruments Buy

    RD 1H 107 M 08 11M PF Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    RK73-RT

    Abstract: RK73G-RT WK73-RT hr r 681k- 1kv A/SG73P1E WK73S2 SG73S2E sec 472m sf MOS2CT52 RK73H-RT
    Text: KOA SPEER ELECTRONICS, INC. passive components 199 Bolivar Drive Bradford, PA 16701 Phone: 814-362-5536 Fax: 814-362-8883 www.koaspeer.com KOA SPEER ELECTRONICS, INC. AHA 12/14 2.5M KOA Speer Electronics, Inc. Printed in U.S.A. passive components KOA Speer’s


    Original     		PDF

    RD 1H 107 M 08 11M PF

    Abstract: No abstract text available
    Text: IS61DDPB21M18A IS61DDPB251236A 1Mx18, 512Kx36 18Mb DDR-IIP Burst 2 CIO Synchronous SRAM (2.5 Cycle Read Latency) FEATURES •                  512Kx36 and 1Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid


    Original     		PDF IS61DDPB21M18A IS61DDPB251236A 1Mx18, 512Kx36 1Mx18 500MHz 450MHz 400MHz RD 1H 107 M 08 11M PF

    Untitled

    Abstract: No abstract text available
    Text: IS61DDP2B22M18A IS61DDP2B21M36A 2Mx18, 1Mx36 36Mb DDR-IIP Burst 2 CIO Synchronous SRAM (2.0 Cycle Read Latency) FEATURES •                   1Mx36 and 2Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid


    Original     		PDF IS61DDP2B22M18A IS61DDP2B21M36A 2Mx18, 1Mx36 2Mx18 400MHz 333MHz 300MHz

    Untitled

    Abstract: No abstract text available
    Text: IS61DDP2B21M18A IS61DDP2B251236A 1Mx18, 512Kx36 18Mb DDR-IIP Burst 2 CIO Synchronous SRAM (2.0 Cycle Read Latency) FEATURES •                   512Kx36 and 1Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid


    Original     		PDF IS61DDP2B21M18A IS61DDP2B251236A 1Mx18, 512Kx36 1Mx18 400MHz 333MHz 300MHz

    Untitled

    Abstract: No abstract text available
    Text: IS61DDP2B21M18A IS61DDP2B251236A 1Mx18, 512Kx36 18Mb DDR-IIP Burst 2 CIO Synchronous SRAM (2.0 Cycle Read Latency) FEATURES •                   512Kx36 and 1Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid


    Original     		PDF IS61DDP2B21M18A IS61DDP2B251236A 1Mx18, 512Kx36 1Mx18 400MHz 333MHz 300MHz

    Untitled

    Abstract: No abstract text available
    Text: IS61DDP2B22M18A IS61DDP2B21M36A 2Mx18, 1Mx36 36Mb DDR-IIP Burst 2 CIO Synchronous SRAM (2.0 Cycle Read Latency) FEATURES •                   1Mx36 and 2Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid


    Original     		PDF IS61DDP2B22M18A IS61DDP2B21M36A 2Mx18, 1Mx36 2Mx18 400MHz 333MHz 300MHz

    Untitled

    Abstract: No abstract text available
    Text: IS61DDPB22M18A IS61DDPB21M36A 2Mx18, 1Mx36 36Mb DDR-IIP Burst 2 CIO Synchronous SRAM (2.5 Cycle Read Latency) FEATURES •                  1Mx36 and 2Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid


    Original     		PDF IS61DDPB22M18A IS61DDPB21M36A 2Mx18, 1Mx36 2Mx18 500MHz 450MHz 400MHz

    Untitled

    Abstract: No abstract text available
    Text: IS61DDPB22M18A IS61DDPB21M36A 2Mx18, 1Mx36 36Mb DDR-IIP Burst 2 CIO Synchronous SRAM (2.5 Cycle Read Latency) FEATURES •                  1Mx36 and 2Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid


    Original     		PDF IS61DDPB22M18A IS61DDPB21M36A 2Mx18, 1Mx36 2Mx18 500MHz 450MHz 400MHz

    Untitled

    Abstract: No abstract text available
    Text: IS61DDPB21M18A IS61DDPB251236A 1Mx18, 512Kx36 18Mb DDR-IIP Burst 2 CIO Synchronous SRAM (2.5 Cycle Read Latency) FEATURES •                  512Kx36 and 1Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid


    Original     		PDF IS61DDPB21M18A IS61DDPB251236A 1Mx18, 512Kx36 1Mx18 500MHz 450MHz 400MHz

    Untitled

    Abstract: No abstract text available
    Text: IS61DDPB22M18A/A1/A2 IS61DDPB21M36A/A1/A2 2Mx18, 1Mx36 36Mb DDR-IIP Burst 2 CIO Synchronous SRAM (2.5 Cycle Read Latency) FEATURES •                  1Mx36 and 2Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid


    Original     		PDF IS61DDPB22M18A/A1/A2 IS61DDPB21M36A/A1/A2 2Mx18, 1Mx36 2Mx18 500MHz 450MHz 400MHz

    Untitled

    Abstract: No abstract text available
    Text: IS61DDP2B22M18A/A1/A2 IS61DDP2B21M36A/A1/A2 2Mx18, 1Mx36 36Mb DDR-IIP Burst 2 CIO Synchronous SRAM (2.0 Cycle Read Latency) FEATURES •                   1Mx36 and 2Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid


    Original     		PDF IS61DDP2B22M18A/A1/A2 IS61DDP2B21M36A/A1/A2 2Mx18, 1Mx36 2Mx18 400MHz 333MHz 300MHz

    Untitled

    Abstract: No abstract text available
    Text: IS61QDP2B41M18A IS61QDP2B451236A 1Mx18 , 512Kx36 18Mb QUAD-P Burst 4 SYNCHRONOUS SRAM (2.0 Cycle Read Latency) FEATURES •                    512Kx36 and 1Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid


    Original     		PDF IS61QDP2B41M18A IS61QDP2B451236A 1Mx18 512Kx36 1Mx18 400MHz 333MHz 300MHz

    Untitled

    Abstract: No abstract text available
    Text: IS61DDPB24M18A/A1/A2 IS61DDPB22M36A/A1/A2 4Mx18, 2Mx36 72Mb DDR-IIP Burst 2 CIO Synchronous SRAM (2.5 Cycle Read Latency) FEATURES •                   2Mx36 and 4Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid


    Original     		PDF IS61DDPB24M18A/A1/A2 IS61DDPB22M36A/A1/A2 4Mx18, 2Mx36 4Mx18 500MHz 450MHz 400MHz

    Untitled

    Abstract: No abstract text available
    Text: IS61DDP2B24M18A/A1/A2 IS61DDP2B22M36A/A1/A2 4Mx18, 2Mx36 72Mb DDR-IIP Burst 2 CIO Synchronous SRAM (2.0 Cycle Read Latency) FEATURES •                   2Mx36 and 4Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid


    Original     		PDF IS61DDP2B24M18A/A1/A2 IS61DDP2B22M36A/A1/A2 4Mx18, 2Mx36 4Mx18 400MHz 333MHz 300MHz

    Untitled

    Abstract: No abstract text available
    Text: IS61QDPB42M18A IS61QDPB41M36A 2Mx18, 1Mx36 36Mb QUAD-P Burst 4 SYNCHRONOUS SRAM (2.5 Cycle Read Latency) FEATURES •                    1Mx36 and 2Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid


    Original     		PDF IS61QDPB42M18A IS61QDPB41M36A 2Mx18, 1Mx36 2Mx18 500MHz 450MHz 400MHz

    Untitled

    Abstract: No abstract text available
    Text: IS61QDP2B41M18A IS61QDP2B451236A 1Mx18 , 512Kx36 18Mb QUAD-P Burst 4 SYNCHRONOUS SRAM (2.0 Cycle Read Latency) FEATURES •                    512Kx36 and 1Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid


    Original     		PDF IS61QDP2B41M18A IS61QDP2B451236A 1Mx18 512Kx36 1Mx18 400MHz 333MHz 300MHz

    IS61DDP2B251236A1

    Abstract: No abstract text available
    Text: IS61DDP2B21M18A/A1/A2 IS61DDP2B251236A/A1/A2 1Mx18, 512Kx36 18Mb DDR-IIP Burst 2 CIO Synchronous SRAM (2.0 Cycle Read Latency) FEATURES •                   512Kx36 and 1Mx18 configuration available.


    Original     		PDF IS61DDP2B21M18A/A1/A2 IS61DDP2B251236A/A1/A2 1Mx18, 512Kx36 1Mx18 400MHz 333MHz 300MHz IS61DDP2B251236A1

    Untitled

    Abstract: No abstract text available
    Text: IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 1Mx18, 512Kx36 18Mb DDR-IIP Burst 2 CIO Synchronous SRAM (2.5 Cycle Read Latency) FEATURES •                  512Kx36 and 1Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid


    Original     		PDF IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2 1Mx18, 512Kx36 1Mx18 500MHz 450MHz 400MHz

    Untitled

    Abstract: No abstract text available
    Text: IS61QDP2B42M18A IS61QDP2B41M36A 2Mx18, 1Mx36 36Mb QUAD-P Burst 4 SYNCHRONOUS SRAM (2.0 Cycle Read Latency) FEATURES •                    1Mx36 and 2Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid


    Original     		PDF IS61QDP2B42M18A IS61QDP2B41M36A 2Mx18, 1Mx36 2Mx18 400MHz 333MHz 300MHz

    Untitled

    Abstract: No abstract text available
    Text: IS61QDPB42M18A IS61QDPB41M36A 2Mx18, 1Mx36 36Mb QUAD-P Burst 4 SYNCHRONOUS SRAM (2.5 Cycle Read Latency) FEATURES •                    1Mx36 and 2Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid


    Original     		PDF IS61QDPB42M18A IS61QDPB41M36A 2Mx18, 1Mx36 2Mx18 500MHz 450MHz 400MHz

    Untitled

    Abstract: No abstract text available
    Text: IS61QDPB41M18A IS61QDPB451236A 1Mx18, 512Kx36 18Mb QUAD-P Burst 4 SYNCHRONOUS SRAM (2.5 Cycle Read Latency) FEATURES •                    512Kx36 and 1Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid


    Original     		PDF IS61QDPB41M18A IS61QDPB451236A 1Mx18, 512Kx36 1Mx18 500MHz 450MHz 400MHz

    Untitled

    Abstract: No abstract text available
    Text: IS61QDP2B42M18A IS61QDP2B41M36A 2Mx18, 1Mx36 36Mb QUAD-P Burst 4 SYNCHRONOUS SRAM (2.0 Cycle Read Latency) FEATURES •                    1Mx36 and 2Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid


    Original     		PDF IS61QDP2B42M18A IS61QDP2B41M36A 2Mx18, 1Mx36 2Mx18 400MHz 333MHz 300MHz

    IS61QDPB42M36A1-450M3I

    Abstract: IS61QDPB42M36A1
    Text: IS61QDPB44M18A/A1/A2 IS61QDPB42M36A/A1/A2 4Mx18, 2Mx36 72Mb QUAD-P Burst 4 SYNCHRONOUS SRAM (2.5 Cycle Read Latency) FEATURES •                    2Mx36 and 4Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid


    Original     		PDF IS61QDPB44M18A/A1/A2 IS61QDPB42M36A/A1/A2 4Mx18, 2Mx36 4Mx18 500MHz 450MHz 400MHz IS61QDPB42M36A1-450M3I IS61QDPB42M36A1

    Untitled

    Abstract: No abstract text available
    Text: IS61QDP2B42M18A/A1/A2 IS61QDP2B41M36A/A1/A2 2Mx18, 1Mx36 36Mb QUAD-P Burst 4 SYNCHRONOUS SRAM (2.0 Cycle Read Latency) FEATURES •                    1Mx36 and 2Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid


    Original     		PDF IS61QDP2B42M18A/A1/A2 IS61QDP2B41M36A/A1/A2 2Mx18, 1Mx36 2Mx18 400MHz 333MHz 300MHz