ic D flip flop 7474
Abstract: T flip flop IC JK flip flop IC ic 7474 features of ic 7474 7474 j-k flip flop pin IC 7474 d flip flop 7474 7474 jk flip flop ic 7474 truth table
Text: INTEGRATED CIRCUITS TTL DUAL JK M A S T E R /S L A V E FLIP FLOP PIN CONNECTION GENERAL DESCRIPTION T O P VIEW The flip flops described herein are TTI, T ra ns is to r-T ra ns is to r Logic dual ]K Ma ster/Slave flip flops. A s y n c h r o r o u s CLEAR in p ut s are provided
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mc10176
Abstract: No abstract text available
Text: MOTOROLA MC10176 H EX " D " M A S T E R -S LA V E FLIP-FLOP The M C 10 17 6 co n ta in s s ix hig h-speed , m aste r sla v e ty p e " D " flip-flops. C lo ck in g is c o m m o n to all s ix flip -flo p s. Data is entered into the m a ste r w h en th e c lo ck is low . M a ste r to s la v e data transfer
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MC10176
MC10176
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Untitled
Abstract: No abstract text available
Text: M M O T O R O L A SN54LS74A SN54LS74A D E S C R I P T I O N - The S N 5 4 L S / 7 4 L S 7 4 A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also complementary
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SN54LS74A
SN54LS74A
SN54LS/74LS74A
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74LS74A
Abstract: No abstract text available
Text: M M O T O R O L A SN54/74LS74A D E S C R I P T I O N - The S N 5 4 L S /7 4 L S 7 4 A dual edge-triggered flip-flop u tilizes Schottky TTL circu itry to produce high speed D-type flip-flops. Each flip-flop has individual cfear and set inputs, arid also com plem entary
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SN54/74LS74A
74LS74A
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Untitled
Abstract: No abstract text available
Text: <8 > M O TO R O LA Military 10531 Dual D Type Master Slave Flip-Flop ELECTRICALLY TESTED PER: MIL-M-38510/06101 T h e 10531 is a dual m a ste r-sla ve typ e D flip -flop. A s yn ch ro n o u s S e t S and R ese t (R) o verrid e C lo ck (C c ) and C lo ck E n a ble ( ¿ e ) inputs. E ach flip -flo p m ay
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MIL-M-38510/06101
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Untitled
Abstract: No abstract text available
Text: M M O T O R O L A MC54F175 MC74F175 QUAD D FLIP-FLOP Q UAD D FLIP-FLOP D E S C R IP T IO N — T he M C 5 4 F /7 4 F 1 7 5 is a h ig h -s p e e d q u a d D flip flo p . T h e d e vice is u s e fu l fo r g e n e ra l flip -flo p r e q u ire m e n ts w h e re
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MC54F175
MC74F175
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Untitled
Abstract: No abstract text available
Text: 74ACT11378 HEX D-TYPE FLIP-FLOP WITH CLOCK ENABLE S C A S 1 8 5 A - A U G U S T 1990 - R EVISED A P R IL 1993 DW OR N PACKAGE • Inputs Are TTL-Voltage Compatible TOP VIEW • Contains Six D-Type Flip-Flops
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74ACT11378
500-mA
300-mil
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74ls534
Abstract: 74LS534N
Text: R C H I I - P S E M IC O N D U C T O R tm DM74LS534 Octal D-Type Flip-Flop With General Description The ’LS534 is a high speed, low pow er octal D-type flip-flop featuring separate D -type inputs fo r each flip-flop and 3-STATE outputs fo r bus oriented applications. A buffered
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DM74LS534
LS534
LS374
74ls534
74LS534N
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MTC 25-16
Abstract: 74LVX112 74LVX112M 74LVX112MTC 74LVX112SJ LVX112 M16A M16D MTC16
Text: A I R C H I I- D S E M IC O N D U C T O R im 74LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear General Description The inputs tolerate voltages up to 7 V allowing the interface of 5V system s to 3 V system s. The LVX112 is a dual J-K Flip-Flop w here each flip-flop has
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74LVX112
LVX112
MTC 25-16
74LVX112
74LVX112M
74LVX112MTC
74LVX112SJ
M16A
M16D
MTC16
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Untitled
Abstract: No abstract text available
Text: 273 54F/74F273 Connection Diagrams Octal D Flip-Flop T— r ' - M R p ~ H rS rz a ht edge-triggered D-type flip-flops with individual D The common buffered Clock CP and Master Reset n ^ re s e i (clear) all flip-flops simultaneously. The register is full
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54F/74F273
54F/74F
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74ls112 pin diagram
Abstract: 74ls112 pin configuration 74LS112 N74S112D 74ls112 function table
Text: 7 4 LS1 1 2 , S 1 1 2 Flip-Flops S ig n e t ic s Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION The '112 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Clock, Set and_Reset inputs. The Set So and Reset (R d) inputs, when LOW,
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1N916,
1N3064,
500ns
500ns
74ls112 pin diagram
74ls112 pin configuration
74LS112
N74S112D
74ls112 function table
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10531
Abstract: E10531 10531/10531/ECL+D+flip+flop
Text: M M O T O R O LA Military 10531 Dual D Type Master Slave Flip-Flop ELECTRICALLY TES T E D PER: M IL-M -38510/06101 T h e 10531 is a d ua l m a ste r-sla ve typ e D flip -flop. A s yn ch ro n o u s S e t (S) and R e s e t (R ) o ve rrid e C lo c k (C c ) a n d C lo c k E n a b le (C g ) inp u ts. E a ch flip -flo p m ay
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Untitled
Abstract: No abstract text available
Text: S E M IC O N D U C T O R 74LVX112 Low Voltage Dual J-K Flip-Flops with Preset and Clear General Description Th e inputs tolerate voltages up to 7V allowing the interface of 5V system s to 3V system s. The LVX112 is a dual J-K Flip-Flop where each flip-flop has
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74LVX112
LVX112
2314-006I
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DDD1173
Abstract: SY100E131 SY10E131
Text: * SYNERGY S E M IC O N D U C T O R SY10E131 SY100E131 4-BIT D FLIP-FLOP FEATURES DESCRIPTION 1100MHz min. toggle frequency The SY10/100E131 are high-speed quad m aster slave D-type flip-flops with differential outputs designed for use in new, high-perform ance ECL system s. The flip -flop s may
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1100MHz
MC10E/100E131
SY10/100E131
suc175
SY10E131JC
J28-1
SY10E131JCTR
SY100E131
DDD1173
SY10E131
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SP9131
Abstract: flip-flop RS 1ECL10131 Pin-for-Pin Compatible with the
Text: SP9131 SP9131 520 MHz DUAL TYPE D MASTER SLAVE FLIP-FLOP The SP9131 is a dual master slave type D flip-flop which is pin-for-pin compatible with the rECL10131, but with improved dynamic performance and increased power dissipation. R-S TRUTH TABLE R S Q„ r1
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SP9131
LC99C
SP9131
1ECL10131,
520MHz
50-ohm
flip-flop RS
1ECL10131
Pin-for-Pin Compatible with the
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7473 JK flip flop
Abstract: IC 74LS73 74LS73D 7473PC 74LS73 dual JK JK flip flop IC Flip-Flop 7473PC pin DIAGRAM OF IC 7473 74LS73 JK JK flip flop IC diagram
Text: 73 CO NNECTIO N DIAGRAM PINOUT A •A /Â 54/7473 ^ /54H /74H 73 O f1014 I/54LS/74LS73 DUAL JK FLIP-FLOP With Separate Clears and Clocks) D E S C R IP TIO N — The ’73 and ’H73 dual JK master/slave flip -flop s have a separate clock fo r each flip -flop . Inputs to the master section are controlled
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f1014
I/54LS/74LS73
54/74H
54/74LS
CLS73)
7473 JK flip flop
IC 74LS73
74LS73D
7473PC
74LS73 dual JK
JK flip flop IC
Flip-Flop 7473PC
pin DIAGRAM OF IC 7473
74LS73 JK
JK flip flop IC diagram
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Untitled
Abstract: No abstract text available
Text: F102311* F10631^ HIGH SPEED DUAL D FLIP-FLOP F10K VOLTAGE COMPENSATED ECL DESCRIPTION - The F10231/F10631 contains two master/slave D-type flip-flops. The internal clock is the O R of two clock inputs, one common to both flip-flops. The O R clock permits the use of one input a s a clock pulse and the other a s an active LO W enable.
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F102311*
F10631^
F10231/F10631
1x222
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IDT74FCT273AT
Abstract: IDT74FCT273CT IDT74FCT273T
Text: IDT74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET FE A T U R E S : D E S C R IP TIO N : - The IDT74FCT273T/AT/CT are octal D flip-flops built using an ad vanced dual metal CMOS technology. The IDT74FCT273T/AT/CThave eight edge-triggered D-type flip-flops with individual D inputs and 0 outputs.
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IDT74FCT273T/AT/CT
-15mA
IDT74FCT273T/AT/CT
IDT74FCT273T/AT/CThave
P20-1)
D20-1)
S020-2)
S020-8)
273AT
273CT
IDT74FCT273AT
IDT74FCT273CT
IDT74FCT273T
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Untitled
Abstract: No abstract text available
Text: TYPES SN74LS377, SN74LS378, SN74LS379 SN54LS377, SN54LS378, SN54LS379 OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH ENABLE O C T O B E R 1976 • R E V IS E D A P R IL 1985 'L S 3 7 7 and 'L S 3 7 8 Contain Eight and S ix Flip-Flops, Respectively, w ith SingleRail O utputs
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SN74LS377,
SN74LS378,
SN74LS379
SN54LS377,
SN54LS378,
SN54LS379
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74HC
Abstract: 74HCT S020 HCT574 74HC-HCT574
Text: 74HC/HCT574 MSI OCTAL D-TYPE FLIP FLOP; POSITIVE EDGE-TRIGGER; 3-STATE F EA TU R ES • • • • G E N E R A L D ES C R IPTIO N The 74H C /H C T 574 are octal O-type flip -flo p s featuring separate D -type inputs fo r each flip -flo p and no n-inverting 3-state
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74HC/HCT574
74HC
74HCT
S020
HCT574
74HC-HCT574
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HCT74
Abstract: lz93 100 pin 74HC 74HCT
Text: 74H C /H C T 74 P H IL IP S IN T E R N A T IO N A L bSE D flip-flops IP H IN ^ v_ DUAL D-TYPE FLIP-FLOP WITH SET AND RESET; POSITIVE-EDGE TRIGGER FEATURES TYPIC AL • O utp u t capability: standard • Ic C cate9orV : flip-flops SYMBOL G E N E R A L D E S C R IP T IO N
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74HC/HCT74
7110fleb
HCT74
lz93 100 pin
74HC
74HCT
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207d
Abstract: 63Q7
Text: SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR S D A S 2 0 7 D -A P R IL 1 9 8 2 - R EVISED MAY 1996 • ALS174 and AS174 Contain Six Flip-Flops With Single-Rail Outputs
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SN54ALS174,
SN54ALS175,
SN54AS174,
SN54AS175B
SN74ALS174,
SN74ALS175,
SN74AS174,
SN74AS175B
ALS174
AS174
207d
63Q7
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F95231
Abstract: No abstract text available
Text: F95231 HIGH SPEED DUAL D FLIP-FLOP D E S C R IP T IO N — T h e F95 2 31 c o n ta in s tw o m a s te r /s la v e D ty p e flip -flo p s . T h e in te r n a l c lo c k is th e OR of tw o c lo ck in p u ts , o n e c o m m o n to b o th flip - flo p s T h e OR c lo c k
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F95231
F95231
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Untitled
Abstract: No abstract text available
Text: F95231 HIGH SPEED DUAL D FLIP-FLOP D E S C R IP T IO N — T h e F 9 5 2 31 c o n ta in s tw o m a s te r /s la v e D ty p e flip -flo p s . T h e in te r n a l c lo ck is th e OR o f tw o c lo ck in p u ts , o n e c o m m o n to b o th flip -flo p s T h e OR c lo c k
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F95231
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