QL3040 IO BLOCK Search Results

QL3040 IO BLOCK Result Highlights (5)

Part	ECAD Model	Manufacturer	Description	Download	Buy
DCL541A01		Toshiba Electronic Devices & Storage Corporation	Digital Isolator / VDD=2.25~5.5V / 150Mbps / 4 channel(F:R=3:1) / Default Output Logic: Low / Input disable
DCL542H01		Toshiba Electronic Devices & Storage Corporation	Digital Isolator / VDD=2.25~5.5V / 150Mbps / 4 channel(F:R=2:2) / Default Output Logic: High / Output enable
DCL541B01		Toshiba Electronic Devices & Storage Corporation	Digital Isolator / VDD=2.25~5.5V / 150Mbps / 4 channel(F:R=3:1) / Default Output Logic: High / Input disable
DCL542L01		Toshiba Electronic Devices & Storage Corporation	Digital Isolator / VDD=2.25~5.5V / 150Mbps / 4 channel(F:R=2:2) / Default Output Logic: Low / Output enable
DCL540H01		Toshiba Electronic Devices & Storage Corporation	Digital Isolator / VDD=2.25~5.5V / 150Mbps / 4 channel(F:R=4:0) / Default Output Logic: High / Output enable

QL3040 IO BLOCK Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
AD 149 AE9 Abstract: AA23 PQ208 QL3040 QL3040-1PB456C QL3040-1PQ208C Text: QL3040 pASIC 3 FPGA Data Sheet •••••• 40,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Device Highlights High Performance & High Density • 40,000 Usable PLD Gates with 252 I/Os • 300 MHz 16-bit Counters, 400 MHz Datapaths	Original	PDF	QL3040 16-bit AD 149 AE9 AA23 PQ208 QL3040-1PB456C QL3040-1PQ208C
CI 3060 elsys Abstract: QL3025-1PQ208C QL3060 QL3060-1PQ208C QL3012 QL3012-1PL84C QL3025 QL3040 QL3040-1PQ208C PL84 Text: Military Plastic pASIC 3 Family Data Sheet • • • • • • 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Device Highlights High Performance & High Density • 60,000 usable PLD gates with 316 I/Os • 300 MHz 16-bit counters, 400 MHz datapaths	Original	PDF	16-bit CI 3060 elsys QL3025-1PQ208C QL3060 QL3060-1PQ208C QL3012 QL3012-1PL84C QL3025 QL3040 QL3040-1PQ208C PL84
QL3004 Abstract: QL3004-1PL68C QL3004E QL3012 QL3004-1PL84C QL3006 QL3025 QL3040 QL3060 Text: pASIC 3 FPGA Family Data Sheet •••••• Up to 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Device Highlights High Performance & High Density • Up to 60,000 usable PLD gates with up to 316 I/Os • 300 MHz 16-bit counters, 400 MHz datapaths	Original	PDF	16-bit QL3004 QL3004-1PL68C QL3004E QL3012 QL3004-1PL84C QL3006 QL3025 QL3040 QL3060
pasic 3 Abstract: QL3004-1PL68C QL3004 QL3004E QL3004-1PL84C QL3006 QL3012 QL3025 QL3040 QL3060 Text: pASIC 3 FPGA Family Data Sheet •••••• Up to 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density Device Highlights High Performance & High Density • Up to 60,000 usable PLD gates with up to 316 I/Os • 300 MHz 16-bit counters, 400 MHz datapaths	Original	PDF	16-bit pasic 3 QL3004-1PL68C QL3004 QL3004E QL3004-1PL84C QL3006 QL3012 QL3025 QL3040 QL3060
QL4090 Abstract: No abstract text available Text: QL12X16B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS …2,000 usable ASIC gates, 88 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.	Original	PDF	QL12X16B 12-by-16 68-pin 84-pin 100-pin 16-bit Synops144-TQFP QL24x32B 208-PQFP QL4090
QL4090 Abstract: pASIC 1 Family 160CQFP 208-CQFP Text: QL16x24B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS …4,000 usable ASIC gates, 122 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.	Original	PDF	QL16x24B 16-by-24 84-pin 100-pin 144-pin 160-pin 16-bit V144-TQFP QL24x32B QL4090 pASIC 1 Family 160CQFP 208-CQFP
74373 latch pin config Abstract: 3-8 decoder 74138 pin diagram ci cd 4058 vhdl code for 74194 QL5064 pin diagram of 74109 7400 TTL QL8x12B-0PL68C 74194 shift register waveform Datasheet ci cd 4058 Text: QuickWorks User’s Guide with SpDE Reference COPYRIGHT INFORMATION Copyright 1991–1999 QuickLogic Corporation. All rights reserved. The information contained in this manual and the accompanying software program are protected by copyright; all rights are reserved by QuickLogic Corporation. QuickLogic	Original	PDF
AF15AF16 Abstract: QL3040 IO block QL3040 Text: QL5232 - QuickPCITM 33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and dual Port SRAM QL5232 - QuickPCI DEVICE HIGHLIGHTS Q8DÃ7Ã±Ã""ÃHCÃ"!ÃivÃqhhÃhqÃhqqr Device Highlights High Performance PCI Controller Q8DÃ8PIUSPGG@S	Original	PDF	QL5232 Hz/32-bit 32-bit 95/98/Win v2144-TQFP QL24x32B 208-PQFP 208-CQFP 125oC AF15AF16 QL3040 IO block QL3040
asynchronous fifo vhdl Abstract: 8 BIT ALU design with verilog/vhdl code full subtractor using ic 74138 74139 for bcd to excess 3 code vhdl code for 8bit bcd to seven segment display 32 BIT ALU design with verilog/vhdl code 74594 16 BIT ALU design with verilog/vhdl code B1516 RAM1024 Text: QuickWorks User Manual with SpDE Reference Release 2009.2.1 Contact Information QuickLogic Corporation 1277 Orleans Drive Sunnyvale, CA 94089 Phone: (408) 990-4000 (US) (905) 940-4149 (Canada) +(44) 1932-57-9011 (Europe) +(852) 2567-5441 (Asia) E-mail: info@quicklogic.com	Original	PDF
baugh-wooley multiplier verilog Abstract: 1BG25 LPQ100 9572xv BC356 LPQ240 block diagram baugh-wooley multiplier 4 BIT ALU design with vhdl code using structural XC3000A actel a1240 Text: LeonardoSpectrum Synthesis and Technology v1999.1 Copyright Copyright 1991-1999 Exemplar Logic, Inc., A Mentor Graphics Company All Rights Reserved Trademarks Exemplar Logic and its Logo are trademarks of Exemplar Logic, Inc. LeonardoSpectrum™, LeonardoInsight™, FlowTabs™, HdlInventor™, SmartScripts™,	Original	PDF	v1999 Index-11 Index-12 baugh-wooley multiplier verilog 1BG25 LPQ100 9572xv BC356 LPQ240 block diagram baugh-wooley multiplier 4 BIT ALU design with vhdl code using structural XC3000A actel a1240