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    1651F

    Abstract: No abstract text available
    Text: MC10E1651 5V, -5VĄECL Dual ECL Output Comparator With Latch The MC10E1651 is fabricated using ON Semiconductor’s advanced MOSAIC IIIt process. The MC10E1651 incorporates a fixed level of input hysteresis as well as output compatibility with 10 KH logic


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    MC10E1651 16-pin 20-pin r14525 MC10E1651/D 1651F PDF

    Untitled

    Abstract: No abstract text available
    Text: MC10E1652 5VĄECL Dual ECL Output Comparator With Latch The MC10E1652 is fabricated using ON Semiconductor’s advanced MOSAIC IIIt process and is output compatible with 10H logic devices. In addition, the device is available in both a 16-pin DIP and a 20-pin surface mount package. However, the MC10E1652 provides


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    MC10E1652 16-pin 20-pin r14525 MC10E1652/D PDF

    E112

    Abstract: E212 MC100E212 MC100E212FN MC100E212FNR2 MC10E212 MC10E212FN MC10E212FNR2
    Text: MC10E212, MC100E212 5VĄECL 3ĆBit Scannable Registered Address Driver The MC10E/100E212 is a scannable registered ECL driver typically used as a fan-out memory address driver for ECL cache driving. In a VLSI array based CPU design, use of the E212 allows the user to


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    MC10E212, MC100E212 MC10E/100E212 MC10E212FN r14525 MC10E212/D E112 E212 MC100E212 MC100E212FN MC100E212FNR2 MC10E212 MC10E212FN MC10E212FNR2 PDF

    Untitled

    Abstract: No abstract text available
    Text: AN1650/D Using WireĆOR Ties in ECLinPS Designs http://onsemi.com APPLICATION NOTE This application note discusses the use of wire-OR ties in EClinPS designs. Theoretical Descriptions of the problems associated with wire-OR ties are included as well as an evaluation and SPICE simulation results. In addition, general guidelines


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    AN1650/D r14525 PDF

    Untitled

    Abstract: No abstract text available
    Text: MC10E411 5VĄECL 1:9 Differential PECL/NECL RAMBus Clock Buffer The MC10E411 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The MC10E411’s function and performance are similar to the popular MC10E111, with the added feature of 1.2 V output swings.


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    MC10E411 MC10E411 MC10E111, MC10E111. r14525 MC10E411/D PDF

    AND8020

    Abstract: MC10E111 MC10E411 MC10E411FN MC10E411FNR2
    Text: MC10E411 5VĄECL 1:9 Differential PECL/NECL RAMBus Clock Buffer The MC10E411 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The MC10E411’s function and performance are similar to the popular MC10E111, with the added feature of 1.2 V output swings.


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    MC10E411 MC10E411 MC10E111, MC10E111. r14525 MC10E411/D AND8020 MC10E111 MC10E411FN MC10E411FNR2 PDF

    TRANSISTOR D 1765 720

    Abstract: E195 MC100E195 MC100E195FN MC100E195FNR2 MC10E195 MC10E195FN MC10E195FNR2
    Text: MC10E195, MC100E195 5VĄECL Programmable Delay Chip The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition. The delay section consists of a chain of gates organized as shown in


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    MC10E195, MC100E195 MC10E/100E195 r14525 MC10E195/D TRANSISTOR D 1765 720 E195 MC100E195 MC100E195FN MC100E195FNR2 MC10E195 MC10E195FN MC10E195FNR2 PDF

    AN1406

    Abstract: LVE111 MC100E111 MC100LVE111 MC100LVE111FN MC100LVE111FNR2
    Text: MC100LVE111 3.3VĄECL 1:9 Differential Clock Driver The MC100LVE111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The MC100LVE111’s function and performance are similar to the popular MC100E111, with the added feature of low voltage operation. It accepts one signal input, which can be


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    MC100LVE111 MC100LVE111 MC100E111, LVE111 r14525 MC100LVE111/D AN1406 MC100E111 MC100LVE111FN MC100LVE111FNR2 PDF

    Untitled

    Abstract: No abstract text available
    Text: MC100LVE111 3.3VĄECL 1:9 Differential Clock Driver The MC100LVE111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The MC100LVE111’s function and performance are similar to the popular MC100E111, with the added feature of low voltage operation. It accepts one signal input, which can be


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    MC100LVE111 MC100E111, LVE111 r14525 MC100LVE111/D PDF

    EL12

    Abstract: MC100LVEL12 MC100LVEL12D
    Text: MC100LVEL12 3.3VĄECL Low Impedance Driver The MC100LVEL12 is a low impedance drive buffer. With two pairs of OR/NOR outputs the device is ideally suited for high drive applications such as memory addressing. The device is functionally equivalent to the EL12 device and operates from a 3.3 V power supply.


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    MC100LVEL12 MC100LVEL12 LVEL12 KVL12it r14525 MC100LVEL12/D EL12 MC100LVEL12D PDF

    Untitled

    Abstract: No abstract text available
    Text: MC10EP196, MC100EP196 Product Preview 3.3V/5VĄECL Programmable Delay Chip with FTUNE The MC10/100EP196 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. It is identical to the


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    MC10EP196, MC100EP196 MC10/100EP196 EP195 EP196 r14525 MC10E196/D PDF

    Untitled

    Abstract: No abstract text available
    Text: MC100EP40 Product Preview 3.3V / 5VĄECL Differential Phase-Frequency Detector The MC100EP40 is a three–state phase–frequency detector intended for phase–locked loop applications which require a minimum amount of phase and frequency difference at lock. Advanced design


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    MC100EP40 r14525 MC100EP40/D PDF

    E112

    Abstract: E212 MC100E112 MC100E112FN MC10E112 MC10E112FN MC10E112FNR2
    Text: MC10E112, MC100E112 5VĄECL Quad Driver The MC10E/100E112 is a quad driver with two pairs of OR/NOR outputs from each gate, and a common, buffered enable input. Using the data inputs the device can serve as an ECL memory address fan-out driver. Using just the enable input, the device serves as a clock


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    MC10E112, MC100E112 MC10E/100E112 MC10E/100E111 MC10E112FNONlit r14525 MC10E112/D E112 E212 MC100E112 MC100E112FN MC10E112 MC10E112FN MC10E112FNR2 PDF

    Untitled

    Abstract: No abstract text available
    Text: MC10EP195, MC100EP195 3.3V / 5VĄECL Programmable Delay Chip The MC10/100EP195 is a programmable delay chip PDC designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and


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    MC10EP195, MC100EP195 MC10/100EP195 EP195 r14525 MC10E195/D PDF

    HEL12

    Abstract: HL12 KEL12 MC10EL12DR2 E112 EL12 MC100EL12 MC10EL12
    Text: MC10EL12, MC100EL12 5VĄECL Low Impedance Driver The MC10EL/100EL12 is a low impedance drive buffer. With two pairs of OR/NOR outputs the device is ideally suited for high drive applications such as memory addressing. The device is a function equivalent to the E112 device with higher performance capabilities.


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    MC10EL12, MC100EL12 MC10EL/100EL12 r14525 MC10EL12/D HEL12 HL12 KEL12 MC10EL12DR2 E112 EL12 MC100EL12 MC10EL12 PDF

    4T SOT23

    Abstract: No abstract text available
    Text: ON Semiconductort MBD301 MMBD301LT1 Silicon Hot-Carrier Diodes SCHOTTKY Barrier Diodes ON Semiconductor Preferred Devices These devices are designed primarily for high–efficiency UHF and VHF detector applications. They are readily adaptable to many other


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    MBD301 MMBD301LT1 MBD301, MMBD301 MMBD301LT1 OT-23 O-236) MMBD301LT3 4T SOT23 PDF

    100LVEL40

    Abstract: AND8020 MC100LVEL40 MC100LVEL40DW MC100LVEL40DWR2
    Text: MC100LVEL40 3.3/5VĄECL Differential Phase-Frequency Detector The MC100LVEL40 is a three state phase frequency–detector intended for phase–locked loop applications which require a minimum amount of phase and frequency difference at lock. Advanced design


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    MC100LVEL40 MC100LVEL40 r14525 MC100LVEL/D 100LVEL40 AND8020 MC100LVEL40DW MC100LVEL40DWR2 PDF

    QEV203

    Abstract: No abstract text available
    Text: QEV 203 SMD 30x25x5 High Frequency VCXO Technical specifications TEMEX TIME & FREQUENCY June 2001, The QEV 203 series is a new range of high frequency VCXO’s @ 622.08 & 666.5143 MHz dedicated to transmission as advanced SDH / SONET applications. These devices are based on high frequency


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    30x25x5 QEV203 08MHz PDF

    Untitled

    Abstract: No abstract text available
    Text: QEV66HF SMD 14.5 x 9.5 x 5.5 High Frequency VCXO Technical specifications TEMEX TIME & FREQUENCY June 2001, The QEV66HF series offers a new range of high frequency VCXO @ 155.52MHz dedicated to transmission as advanced SDH / SONET applications. This device is using inverted-MESA Xtal typically at


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    QEV66HF QEV66HF 52MHz 52MHz PDF

    Temex qev

    Abstract: QEV110 110 SMD
    Text: QEV 110 SMD 20 x 13 x 10 High Frequency VCXO Technical specifications TEMEX TIME & FREQUENCY June 2001, The QEV 110 series is a new range of high frequency VCXO’s @ 622.08 & 666.5143 MHz dedicated to transmission as advanced SDH / SONET applications. These devices are based on high frequency


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    QEV110 08MHz Temex qev 110 SMD PDF

    mini lvds

    Abstract: Temex lvds
    Text: QEV66HF SMD 14.5 x 9.5 x 5.5 High Frequency VCXO Technical specifications TEMEX TIME & FREQUENCY June 2001, The QEV66HF series offers a new range of high frequency VCXO @ 155.52MHz dedicated to transmission as advanced SDH / SONET applications. This device is using inverted-MESA Xtal typically at


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    QEV66HF QEV66HF 52MHz 52MHz mini lvds Temex lvds PDF

    1N3890A

    Abstract: 1N3891A 1N3893A
    Text: Dim Inches M illim eter Minimum Maximum Minimum Maximum N otes Notes: 1. 1 0 - 3 2 UNF3A th re ad s 2. Full th re ad s w ithin 2 1 /2 th re ad s 3. S tandard P olarity: Stud is Cathode Reverse P olarity: Stud is Anode M icrosem i C atalog Num ber Working Peak


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    1N3890A 1N3893A 1N3890A* 1N3891A* 1N3893A* D0203AA 1N3891A 1N3893A PDF

    SBR3060

    Abstract: No abstract text available
    Text: 30 Amp Schottky Rectifier SBR3060 Dim Inches M illim eter Minimum Maximum Minimum Maximum N otes Notes: 1. 1 0 - 3 2 UNF3A th re ad s 2. Full th re ad s w ithin 2 1 /2 th re ad s 3. S tandard P olarity: Stud is Cathode. Reverse P o la rity Stud is Anode M icrosem i


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    SBR3060 D0203AA SBR3060* SBR3060 PDF

    1N3890

    Abstract: 1N3891 1N3893 1N3890 JAN
    Text: Military Fast Recovery Rectifier 1N3t 90 i f ^3893 Dim Inches M illim eter Minimum Maximum Minimum Maximum N otes Notes: 1. 1 0 - 3 2 UNF3A th re ad s 2. Full th re ad s w ithin 2 1 /2 th re ad s 3. S tandard P olarity: Stud is Cathode Reverse P olarity: Stud is


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    1N3890* 1N3891* 1N3893* D0203AA 1N3890 1N3893 1N3890 1N3891 1N3893 1N3890 JAN PDF