PLL10 Search Results

400ps a2

Abstract: PLL102-108
Contextual Info: PLL102-108 Programmable DDR Zero Delay Clock Driver FEATURES • • • • • • PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz. Distributes one clock Input to one bank of ten differential outputs. Track spread spectrum clocking for EMI reduction.

PLL103-11

Contextual Info: PLL103-11 Low Skew Buffers FEATURES • • • Generates 13 copies of High-speed clock inputs. Supports up to three SDRAM DIMMS synchronous clocks. Supports 2-wire I2C serial bus interface with readback. 50% duty cycle with low jitter. Less than 5ns delay.

Contextual Info: PLL1070A 9939 Via Pasar • San Diego, CA 92126 TEL 858 621-2700 FAX (858) 621-2722 PHASE LOCKED LOOP Rev A PHASE NOISE (1 Hz BW, typical) FEATURES • Frequency Range: 1055 - 1105 MHz • Step Size: 30 KHz • PLL - Style Package APPLICATIONS • Basestations

PLL103-53

Abstract: DDR6
Contextual Info: Preliminary PLL103-53 DDR SDRAM Buffer with 5 DDR or 3 SDR/3 DDR DIMMS FEATURES • • • Generates 30-output buffers from one input. Supports up to 4 DDR DIMMS or 3 SDR DIMMS and 2 DDR DIMMS. Supports 266MHz DDR SDRAM. One additional output for feedback.

PLL103-01

Contextual Info: PLL103-01 Low Skew Buffers FEATURES • • • Generate 18 copies of High-speed clock inputs. Supports up to four SDRAM DIMMS synchronous clocks. Supports 2-wire I2C serial bus interface with readback. 50% duty cycle with low jitter. Less than 5ns delay.

PLL103-06

Abstract: PLL202-04
Contextual Info: Preliminary PLL103-06 DDR SDRAM Buffer with 2 DDR or 3 SDRAM DIMMS FEATURES • • • Generates 12-output buffers from one input. Supports up to 2 DDR DIMMS or 3 SDRAM DIMMS. Supports 266MHz DDR SDRAM. One additional output for feedback. Less than 5ns delay.

PLL103-05

Contextual Info: Preliminary PLL103-05 1-to-5 Clock Distribution Buffer FEATURES 5 outputs identical to FIN. Low skew < 250 ps between outputs . Input / Output frequency range 0 – 160 MHz 25mA drive capability at TTL levels. 70mA drive capability at CMOS levels. 3.3V operation.

PLL103-04

Contextual Info: Preliminary PLL103-04 1-to-4 Clock Distribution Buffer FEATURES • • 4 outputs identical to FIN. Low skew < 250 ps between outputs . Input / Output frequency range 0 – 160 MHz 25mA drive capability at TTL levels. 70mA drive capability at CMOS levels.

ddr5

Abstract: PLL103-02 PLL202-04
Contextual Info: PLL103-02 DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS FEATURES • • • Generates 24 output buffer from one input. Supports up to four DDR DIMMS or 2 SDRAM DIMMS. Supports 266MHz DDR SDRAM. One additional output for feedback. Less than 5ns delay.

AN-200

Abstract: AN-201 AN-202 PLL1045A OSC-40MHZ
Contextual Info: PLL1045A 9939 Via Pasar • San Diego, CA 92126 TEL 858 621-2700 FAX (858) 621-2722 PHASE LOCKED LOOP Rev A1 PHASE NOISE (1 Hz BW, typical) FEATURES • Frequency Range: 1020 - 1070 MHz • Step Size: 30 KHz • PLL - Style Package APPLICATIONS • Basestations

1055

Abstract: AN-200 AN-201 AN-202 PLL1070A
Contextual Info: PLL1070A 9939 Via Pasar • San Diego, CA 92126 TEL 858 621-2700 FAX (858) 621-2722 PHASE LOCKED LOOP Rev A PHASE NOISE (1 Hz BW, typical) FEATURES • Frequency Range: 1055 - 1105 MHz • Step Size: 30 KHz • PLL - Style Package APPLICATIONS • Basestations

m16811

Abstract: u48 PMU ICS952501 BT135 1001 dl pwm quanta T210P 12Bst MAX8863SEUK T quanta computer
Contextual Info: 1 2 3 4 5 6 CPUCLK+ CPUCLK- Power - Source Control HCLK+ HCLK- CPU CORE Power PAGE 41. PAGE 38. PCLK_MPCI ICS952501 (PLL202-108) PCLK_1394 MCLK PCLK_591 A PCLK_SB CLOCKS buffer (ICS93735) (PLL102-108) GCLK PAGE 40. PCI BUS Routing Table =

ICS553

Abstract: P102 PLL102-04 PLL102-15 buffer DT2
Contextual Info: PLL102-15 Low Skew Output Buffer FEATURES • • • • • • • Frequency range 25 ~ 60MHz. Internal phase locked loop will allow spread spec trum modulation on reference clock to pass to the outputs up to 33kHz SST modulation . Zero input - output delay.

ddr4t

Abstract: PLL103-02 PLL103-02XC PLL103-02XC-R
Contextual Info: PLL103-02 DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS FEATURES • • • • • • • • • PIN CONFIGURATION Generates 24 output buffers from one input. Supports up to four DDR DIMMS. Supports 266MHz DDR SDRAM. One additional output for feedback.

PLL102-04SCL-R

Abstract: P102-04SC PLL102-04 PLL102-04SC PLL102-04SCL PLL102-04SC-R
Contextual Info: PLL102-04 Low Skew Output Buffer FEATURES • • Frequency range 50 ~ 120MHz. Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to the outputs up to 100kHz SST modulation . Zero input - output delay. Less than 700 ps device - device skew.

P102-05SC

Abstract: PLL102-05 PLL102-05SC PLL102-05SCL PLL102-05SCL-R PLL102-05SC-R
Contextual Info: PLL102-05 Low Skew Output Buffer FEATURES • • • • • • • Frequency range 25 ~ 60MHz. Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to the outputs up to 100kHz SST modulation . Zero input - output delay.

MPC932P

Contextual Info: PLL102-01 Low Voltage PLL Clock Drivers Q5 VCCO VSSO Q4 VCCO Q3 25 24 23 22 21 20 19 18 17 16 VCCQ0 26 15 QFB Q0 27 14 VCCO_QFB VSSO 28 SD1:2 29 SD0 VSS0_QFB 13 FB_IN 12 SD3 30 11 SD4 MODE 31 10 VCCA 32 9 SD5 VSSA 1 2 3 4 5 6 7 8 FBSEL0 FBSEL1 MR/OE COM_SD

phase locked loop

Abstract: AN-201 AN-200 AN-202 PLL1000A
Contextual Info: PLL1000A 9939 Via Pasar • San Diego, CA 92126 TEL 858 621-2700 FAX (858) 621-2722 PHASE LOCKED LOOP Rev A PHASE NOISE (1 Hz BW, typical) FEATURES • Frequency Range: 988 - 1028 MHz • Step Size: 1000 KHz • PLL - Style Package APPLICATIONS • Basestations

PLL102-109

Contextual Info: Preliminary PLL102-109 Programmable DDR Zero Delay Clock Driver FEATURES • • • • • • PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz. Distributes one clock Input to one bank of six differential outputs. Track spread spectrum clocking for EMI reduction.

PLL103-07

Abstract: PLL202-04
Contextual Info: Preliminary PLL103-07 2 DIMM DDR Fanout Buffer FEATURES Generates 12-output buffers from one input. Supports VIA Pro266 DDR chipset. Supports up to 2 DDR DIMMS. Supports up to 400MHz DDR, SDRAMS. One additional output for feedback. 6 differential clock distribution.

ddr5

Abstract: PLL103-02 PLL202-04 ddr-7-t
Contextual Info: PLL103-02 Rev.D DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS FEATURES Generates 24 output buffer from one input. Supports up to four DDR DIMMS. Supports 266MHz DDR SDRAM. One additional output for feedback. Less than 5ns delay. Skew between any outputs is less than 100 ps.

PLL103-03

Abstract: PLL202-04
Contextual Info: Preliminary PLL103-03 DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS FEATURES • • • Generates 24-output buffers from one input. Supports up to 4 DDR DIMMS or 3 SDR DIMMS and 2 DDR DIMMS. Supports 266MHz DDR SDRAM. One additional output for feedback.

P102-10SC

Abstract: PLL102-10 PLL102-10SC PLL102-10SC-R
Contextual Info: PLL102-10 Low Skew Output Buffer FEATURES • • Frequency range 50 ~ 120MHz. Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to outputs. Zero input - output delay. Less than 700 ps device - device skew. Less than 250 ps skew between outputs.

P102-03SC

Abstract: PLL102-03 PLL102-03SC PLL102-03SCL PLL102-03SCL-R PLL102-03SC-R
Contextual Info: PLL102-03 Low Skew Output Buffer FEATURES • • Frequency range 75 ~ 180MHz. Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to the outputs up to 100kHz SST modulation . Zero input - output delay. Less than 700 ps device - device skew.