PLL FOR 144 MHZ Search Results

PLL FOR 144 MHZ Result Highlights (5)

Part	Manufacturer	Description
GCM188D70E226ME36D	Murata Manufacturing Co Ltd	Chip Multilayer Ceramic Capacitors for Automotive
GRM022C71A472KE19L	Murata Manufacturing Co Ltd	Chip Multilayer Ceramic Capacitors for General Purpose
GRM033C81A224KE01W	Murata Manufacturing Co Ltd	Chip Multilayer Ceramic Capacitors for General Purpose
GRM155D70G475ME15D	Murata Manufacturing Co Ltd	Chip Multilayer Ceramic Capacitors for General Purpose
GRM155R61J334KE01D	Murata Manufacturing Co Ltd	Chip Multilayer Ceramic Capacitors for General Purpose

PLL FOR 144 MHZ Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
M2032 Abstract: M513 MAVC-060000-100144 Text: Synthesizer , SMT Fixed Frequency, 144 MHz MAVC-060000-100144 Rev: A Features ♦ ♦ ♦ ♦ ♦ RoHS Compliant Fully Integrated VCO, PLL, Loop Filter High Performance, Low Cost Miniature SMT Package LSM6 Includes microcontroller for PLL programming Description	Original	PDF	MAVC-060000-100144 ISO9001 M2032 M513 MAVC-060000-100144
Untitled Abstract: No abstract text available Text: CY7C1648KV18 CY7C1650KV18 144-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) Features • JTAG 1149.1 compatible test access port Phase locked loop (PLL) for accurate data placement	Original	PDF	CY7C1648KV18 CY7C1650KV18 144-Mbit 450-MHz
Untitled Abstract: No abstract text available Text: CY7C1648KV18 CY7C1650KV18 144-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) Features • JTAG 1149.1 compatible test access port ■ Phase locked loop (PLL) for accurate data placement	Original	PDF	CY7C1648KV18 CY7C1650KV18 144-Mbit 450-MHz
3M Touch Systems Abstract: No abstract text available Text: CY7C1648KV18 CY7C1650KV18 144-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.0 Cycle Read Latency 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) Features • JTAG 1149.1 compatible test access port ■ Phase locked loop (PLL) for accurate data placement	Original	PDF	CY7C1648KV18 CY7C1650KV18 144-Mbit 450-MHz 3M Touch Systems
CY7C1665KV18 Abstract: 3M Touch Systems Text: CY7C1663KV18, CY7C1665KV18 144-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 144-Mbit QDR ® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features • JTAG 1149.1 compatible test access port ■ Phase locked loop (PLL) for accurate data placement	Original	PDF	144-Mbit CY7C1663KV18, CY7C1665KV18 550-MHz CY7C1665KV18 3M Touch Systems
Untitled Abstract: No abstract text available Text: CY7C1663KV18/CY7C1665KV18 144-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 144-Mbit QDR ® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features • JTAG 1149.1 compatible test access port ■ Phase locked loop (PLL) for accurate data placement	Original	PDF	CY7C1663KV18/CY7C1665KV18 144-Mbit 550-MHz CY7C1665KV18
3M Touch Systems Abstract: No abstract text available Text: CY7C1663KV18, CY7C1665KV18 144-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 144-Mbit QDR ® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features • JTAG 1149.1 compatible test access port ■ Phase locked loop (PLL) for accurate data placement	Original	PDF	144-Mbit CY7C1663KV18, CY7C1665KV18 550-MHz 3M Touch Systems
Untitled Abstract: No abstract text available Text: Surface Mount Voltage Controlled Oscillator 5V Tuning for PLL IC’s ROS-1000PV+ 900 to 1000 MHz Features •฀low฀phase฀noise,฀-144฀dBc/Hz฀at฀1฀MHz,฀typ. •฀linear฀tuning,฀27-38฀MHz/V฀typ. •฀aqueous฀washable CASE STYLE: CK605	Original	PDF	ROS-1000PV+ CK605
Untitled Abstract: No abstract text available Text: NON-CATALOG Surface Mount Voltage Controlled Oscillator 5V Tuning for PLL IC’s ROS-1000PV 900 to 1000 MHz Features • low phase noise, -144 dBc/Hz at 1 MHz, typ. • linear tuning, 27-38 MHz/V typ. • aqueous washable CASE STYLE: CK605 PRICE: Contact Sales Dept.	Original	PDF	ROS-1000PV CK605
Untitled Abstract: No abstract text available Text: Surface Mount Voltage Controlled Oscillator 5V Tuning for PLL IC’s ROS-1000PV+ 900 to 1000 MHz Features • low phase noise, -144 dBc/Hz at 1 MHz, typ. • linear tuning, 27-38 MHz/V typ. • aqueous washable CASE STYLE: CK605 PRICE: $19.95 ea. QTY 5-49	Original	PDF	ROS-1000PV+ CK605
Untitled Abstract: No abstract text available Text: Surface Mount ROS-1000PV+ ROS-1000PV Voltage Controlled Oscillator 5V Tuning for PLL IC's 900 to 1000 MHz Features • low phase noise, -144 dBc/Hz at 1 MHz, typ. • linear tuning, 27-38 MHz/V typ. • aqueous washable CASE STYLE: CK605 PRICE: $19.95 ea. QTY 5-49	Original	PDF	ROS-1000PV+ ROS-1000PV CK605 2002/95/EC) ROS-1000PV
ROS-1000PV Abstract: 1000PV PL-012 Text: ROS-1000PV+ ROS-1000PV Surface Mount Voltage Controlled Oscillator 5V Tuning for PLL IC’s 900 to 1000 MHz Features • low phase noise, -144 dBc/Hz at 1 MHz, typ. • linear tuning, 27-38 MHz/V typ. • aqueous washable CASE STYLE: CK605 PRICE: $19.95 ea. QTY 5-49	Original	PDF	ROS-1000PV+ ROS-1000PV CK605 2002/95/EC) ROS-1000PV 1000PV PL-012
PL-012 Abstract: ROS-1000PV Text: ROS-1000PV+ ROS-1000PV Surface Mount Voltage Controlled Oscillator 5V Tuning for PLL IC’s 900 to 1000 MHz Features • low phase noise, -144 dBc/Hz at 1 MHz, typ. • linear tuning, 27-38 MHz/V typ. • aqueous washable CASE STYLE: CK605 PRICE: $19.95 ea. QTY 5-49	Original	PDF	ROS-1000PV+ ROS-1000PV CK605 2002/95/EC) PL-012 ROS-1000PV
PL-012 Abstract: ROS-1000PV Text: ROS-1000PV+ ROS-1000PV Surface Mount Voltage Controlled Oscillator 5V Tuning for PLL IC’s 900 to 1000 MHz Features • low phase noise, -144 dBc/Hz at 1 MHz, typ. • linear tuning, 27-38 MHz/V typ. • aqueous washable CASE STYLE: CK605 PRICE: $19.95 ea. QTY 5-49	Original	PDF	ROS-1000PV+ ROS-1000PV CK605 2002/95/EC) PL-012 ROS-1000PV

eMIOS channel is set up to drive the eTPU Abstract: No abstract text available Text: SPC563M60L5 SPC563M60B2 32-bit Power Architecture based MCU for automotive powertrain applications Preliminary Data Features • Fully static operation, 0 MHz - 80 MHz plus 2% frequency modulation - 82 MHz ■ -40 °C to 150 °C junction temperature ■	Original	PDF	SPC563M60L5 SPC563M60B2 32-bit eMIOS channel is set up to drive the eTPU
TFBGA_78 Abstract: No abstract text available Text: QL58x0 Enhanced QuickPCI Target Family Data Sheet • • • • • • 33/66 MHz/32-bit PCI Target with Embedded Programmable Logic, Embedded Computational Units, and Dual Port SRAM Device Highlights High Performance PCI Controller • 33/66 MHz 32-bit PCI Target	Original	PDF	QL58x0 Hz/32-bit 32-bit 95/98/2000/NT 484-ball TFBGA_78
LVCMOS25 Abstract: FAR Family C4 Series P-Q type Text: QL58x0 Enhanced QuickPCI Target Family Data Sheet • • • • • • 33/66 MHz/32-bit PCI Target with Embedded Programmable Logic, Embedded Computational Units, and Dual Port SRAM Device Highlights High Performance PCI Controller • 33/66 MHz 32-bit PCI Target	Original	PDF	QL58x0 Hz/32-bit 32-bit 95/98/2000/NT LVCMOS25 FAR Family C4 Series P-Q type
k3934 Abstract: PH90 STM-16 PH180 Text: 2.5 Gbit/s Clock and Data Recovery Circuit GD16506 Advance Information General Description Features The 155 MHz output clock is maintained within 500 ppm tolerance even in absence of data. The GD16506 is a high performance monolithic integrated 2.2 to 2.7 Gbit/s	Original	PDF	GD16506 GD16506 STM-16 OC-48. DK-2740 k3934 PH90 STM-16 PH180
pH 4 n Abstract: eea 2231 PH90 STM-16 bang bang phase detector ph-180 Text: 2.5 Gbit/s Clock and Data Recovery Circuit GD16506 Advance Information General Description Features The 155 MHz output clock is maintained within 500 ppm tolerance even in absence of data. The GD16506 is a high performance monolithic integrated 2.2 to 2.7 Gbit/s	Original	PDF	GD16506 GD16506 STM-16 OC-48. DK-2740 pH 4 n eea 2231 PH90 STM-16 bang bang phase detector ph-180
tfBGA PACKAGE thermal resistance Abstract: No abstract text available Text: QL58x0 Enhanced QuickPCI Target Family Data Sheet • • • • • • 33/66 MHz/32-bit PCI Target with Embedded Programmable Logic, Embedded Computational Units, and Dual Port SRAM Device Highlights High Performance PCI Controller • 33/66 MHz 32-bit PCI Target	Original	PDF	QL58x0 Hz/32-bit 32-bit 95/98/2000/NT 484-ballnformation tfBGA PACKAGE thermal resistance
LVCMOS25 Abstract: No abstract text available Text: QL58x0 Enhanced QuickPCI Target Family Data Sheet • • • • • • 33/66 MHz/32-bit PCI Target with Embedded Programmable Logic, Embedded Computational Units, and Dual Port SRAM Device Highlights Extendable PCI Functionality High Performance PCI Controller	Original	PDF	QL58x0 Hz/32-bit 32-bit LVCMOS25
U4257bm Abstract: U4257 A2401 Text: Features • • • • • • • • • • • • AM/FM Tuner Front End with Integrated PLL AM Up-conversion System AM-IF: 10.7 MHz FM Down-conversion System (FM-IF: 10.7 MHz) IF Frequencies up to 25 MHz Fine-tuning Steps: AM = 1 kHz and FM = 50 kHz/25 kHz/12.5 kHz	Original	PDF	Hz/25 Hz/12 T4260 T4260 4528C U4257bm U4257 A2401
U4257bm Abstract: U4257 U4257B 4528D S391D FM receiver integrated circuit automatic tune sw1 band sw2 receiver am mw B123 B140 B141 Text: Features • • • • • • • • • • • • AM/FM Tuner Front End with Integrated PLL AM Up-conversion System AM-IF: 10.7 MHz FM Down-conversion System (FM-IF: 10.7 MHz) IF Frequencies up to 25 MHz Fine-tuning Steps: AM = 1 kHz and FM = 50 kHz/25 kHz/12.5 kHz	Original	PDF	Hz/25 Hz/12 T4260 T4260 4528D U4257bm U4257 U4257B S391D FM receiver integrated circuit automatic tune sw1 band sw2 receiver am mw B123 B140 B141
3.686 MHZ Abstract: ICD2028 23967 IC 40007 Text: ICD2028 PC Motherboard Clock Generator Features Functional Description • Eight independent dock outputs handle all clocking requirements for personal computer motherboards • CPU clock frequency range: 10 MHz to 100 MHz with user-defined duty cycle • Four user-configurable outputs	OCR Scan	PDF	ICD2028 20-pin 000t1] CPU/212] 3.686 MHZ 23967 IC 40007

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PLL FOR 144 MHZ Search Results

PLL FOR 144 MHZ Result Highlights (5)

PLL FOR 144 MHZ Datasheets Context Search

M2032

Untitled

Untitled

3M Touch Systems

CY7C1665KV18

Untitled

3M Touch Systems

Untitled

Untitled

Untitled

Untitled

ROS-1000PV

PL-012

PL-012

eMIOS channel is set up to drive the eTPU

TFBGA_78

LVCMOS25

k3934

pH 4 n

tfBGA PACKAGE thermal resistance

LVCMOS25

U4257bm

U4257bm

3.686 MHZ