PIN CONFIGURATION OF LOGIC GATES Search Results

Contextual Info: Signetics 82S153A PLS153A Field Programmable Logic Array (18x42x10) Military Customer Specific Products Signetics Programmable Logic Product Specification PIN CONFIGURATION DESCRIPTION FEATURES The 82S153A is a two-level logic element, consisting of 42 A N D gates and 10 O R

26 SIGNETICS

Contextual Info: S ig n e t ic s PLS173 Field-Programmable Logic Array 22x42x10 Military Application Specific Products Slgnetlcs Programmable Logic Product Specification PIN CONFIGURATION DESCRIPTION FEATURES The PLS173 is a two-level logic element consisting of 42 AND gates and 10 OR

L5472

Abstract: L2688 L5568
Contextual Info: r x / i r * ! MICROELECTRONICS XL78C800 Multi-Level E2PLDs PIN CONFIGURATION FEATURES • ■ ■ CLK/I [ Advanced ERASIC Architecture — True gate array style logic integration — From 1 to 42 internal logic levels without using a pin — Eliminates 2-level logic restriction of

Contextual Info: MITSUBISHI ASTTLs pS?< M74AS20P DUAL 4 -INPUT POSITIVE NAND G ATE DESCRIPTION PIN CONFIGURATION TOP VIEW The M74AS20P is a semiconductor integrated circuit consisting of two 4-input positive-logic NAND gates, us­ able as negative-logic NOR gates. FEATURES

74AS1804

Contextual Info: MITSUBISHI ASTTLs -*00°° M 74AS1804P HEX 2-INPUT NAND DRIVER DESCRIPTION The M74AS1804P is a semiconductor integrated circuit consisting of six 2-input positive-logic NAND buffer gates, usable as negative-logic NOR buffer gates. PIN CONFIGURATION TOP VIEW

74AS1000

Contextual Info: MITSUBISHI A STTLs M 74AS1000AP QUADRUPLE 2-INPUT POSITIVE NAND DRIVER DESCRIPTION PIN CONFIGURATION TOP VIEW The M74AS1000AP is a semiconductor integrated circuit consisting of four 2-input positive-logic NAND buffer gates, usable as negative-logic NOR buffer gates.

M74AS02P

Contextual Info: MITSUBISHI ASTTLs M74AS02P ŸŸ& 0 QUADRUPLE 2-INPUT POSITIVE NOR GATE DESCRIPTION PIN CONFIGURATION TOP VIEW The M74AS02P is a semiconductor integrated circuit consisting of four 2-input positive-logic NOR gates, us­ able as negative-logic NAND gates.

plhs18p8

Contextual Info: Signetics PLHS18P8A Programmable AND Array Logic 18x72x8 Military Standard Products Product Specification PIN CONFIGURATION DESCRIPTION FEATURES The PLHS18P8A is a two-level logic ele­ ment consisting of 72 AND gates and 8 OR gates with fusible connections for pro­

Contextual Info: PLS173 Slgnetics Field-Programmable Logic Array 22x42x10 Military Application Specific Products Signetics Programmable Logic Product Specification PIN CONFIGURATION DESCRIPTION FEATURES T h e P L S 1 7 3 is a two-level logic elem ent consisting of 4 2 A N D gates and 10 O R

Contextual Info: MITSUBISHI ASTTLs M74AS08P QUADRUPLE 2-INPUT POSITIVE AND GATE DESCRIPTION PIN CONFIGURATION TOP VIEW The M74AS08P is a semiconductor integrated circuit consisting of four 2-input positive-logic AND gates, us­ able as negative-logic OR gates. FEATURES • High speed

logic gates pin configuration

Abstract: PLHS18P8A pin configuration of logic gates logic gates pin configuration and
Contextual Info: Product specification Signetics Military Standard Products Programmable AND array logic 18 x 72 x 8 PIN CONFIGURATION DESCRIPTION FEATURES The PLHS18P8A is a two-level logic element consisting of 72 AND gates and 8 OR gates with fusible connections for programming I/O

plus405

Abstract: pin diagram of TVC 2 HB
Contextual Info: PLUS405 Signetics Field-Programmable Logic Sequencer 16x64x8 Military Application Specific Products Signetics Programmable Logic Product Specification • Series 28 PIN CONFIGURATION DESCRIPTION FEATURES The PLUS405 device is a bipolar pro­ grammable state machine of the Mealy

plhs18p8

Abstract: PLHS18 PLHS18P8A
Contextual Info: Signetics Military Standard Products PLHS18P8A Programmable AND Array Logic 18x72x8 Product Specification PIN CONFIGURATION DESCRIPTION FE A TU R E S The PLHS18P8A is a two-level logic ele­ ment consisting of 72 ANDgates and SOR gates with fusible connections for pro­

Contextual Info: MITSUBISHI HIGH S P E E D CMOS M74HC20P M74HC20DP DUAL 4-INPUT POSITIVE NAND GATE DESCRIPTION The M74HC20 is a semiconductor integrated circuit con­ PIN CONFIGURATION TOP VIEW sisting of two 4-input positive-logic NAND, usable as nega­ tive-logic NOR gates.

M74F00P

Contextual Info: i b54Tña7 ODlMOäS E ,*oOo c ' I MITSUBISHI ADVANCED SCHOTTKY TTL M 74F00P/FP/DP niTSUBISHI íDGTL LOGIC} Ó7E t ; QUADRUPLE 2-IN PU T POSITIVE NAND GATE DESCRIPTION PIN CONFIGURATION TOP VIEW The M 74F00P is a semiconductor integrated circuit con­ sisting of four 2-i'nput positive-logic NAND gates, usable

Contextual Info: D E I MITSUBISHI íDGTL LOGIC} TI ^ 2 ^ 0 2 7 1 G D lE lñ b |~ “ MITSUBISHI ASTTLs M74AS32P ,*o O 7-Y3-.SQUADRUPLE 2-INPUT POSITIVE OR GATE DESCRIPTION PIN CONFIGURATION TOP VIEW The M74AS32P is a semiconductor integrated circuit consisting of tour 2-input positive-logic OR gates, us­

G4849

Contextual Info: PLUS405 Signetics Field-Programmable Logic Sequencer 16 x 64 x 8 Military Application Specific Products Signetics Programmable Logic Product Specification • Series 28 PIN CONFIGURATION DESCRIPTION FEATURES Th e P LU S 405 device is a bipolar pro­ gram m able state m achine of the M ealy

Contextual Info: GD54/74LS14 HEX SCHMITT-TRIGGER INVERTERS Description Pin Configuration This device contains six independent gates each of which performs the logic INVERT function. Each in­ put has hysteresis which increases the noise im­ munity and transforms a slowly changing input signal

74LS14 oscillator 4 Mhz

Abstract: 74ls14 pin configuration 74LS14 function table pin configuration 74LS14 74ls14 ttl 74ls14 74LS TTL Oscillator 54LS 74LS IN3064
Contextual Info: GD54/74LS14 HEX SCHMITT-TRIGGER INVERTERS Description Pin Configuration This device contains six independent gates each of which performs the logic INVERT function. Each in­ put has hysteresis which increases the noise im­ munity and transforms a slowly changing input signal

Contextual Info: GD54/74LS14 HEX SCHMITT-TRIGGER INVERTERS Description Pin Configuration This device contains six independent gates each of which perforins th logic INVERT function. Each in­ put has hysteresis which increases the noise im­ munity and tr&nsfotms a slowly changing Input signal

Contextual Info: GD54/74S51 DUAL 2-WIDE 2-INPUT AND-OR-INVERT GATES Description Pin Configuration This device contains two independent combinations of gates each of which performs the logic AND-ORINVERT function. MAKE N O EXTERNAL CO NNECTIO N V Cc 1B 1D 1C 1Y Y=AB+C D Function Table

74ls145

Contextual Info: GD54/74LS145 BCD-TO-DECIMAL DECODER/DRIVER Features Pin Configuration • Full Decoding of Input Logic • 80-mA Sink-Current Capability • All Outputs Are Off for Invalid BCD Input Con­ ditions • Low Power Dissipation of ’LS145.35 mW Typical INPUTS

74LS10 mitsubishi

Contextual Info: M IT S U B IS H I HIGH SPEED CMOS M74HC10P/FP/DP T R IP L E 3 -IN P U T P O S IT IV E NAND GATE DESCRIPTION PIN CONFIGURATION TOP VIEW The M74HC10 is a semiconductor integrated circuit con­ sisting of three 3-input positive-logic NAND gates, usable as negative-logic NOR gates.

Contextual Info: MITSUBISHI ALSTTLs _ MITSUBI SHI -CDGTL LOGIC} 11 M 74ALS1 0 2 0 AP deJ hSMTaev üaiavati 4 | DUAL 4-IN P U T POSITIVE NAND BUFFER - 7 ^ ' Y 3 ~ / S ’ DESCRIPTION PIN CONFIGURATION TOP VIEW The M74ALS1020AP is a semiconductor integrated cir­ cuit consisting of two 4-input positive-logic NAND buffer