PIN CONFIGURATION 74LS13 Search Results

and gate 74LS138

Abstract: SP74HCT138N TTL 74ls138 74LS138 LOGIC OF 74LS138 pin for 74LS138 74LS138 pin configuration SP74HCT138 SP74HCT138J 74LS138 pin
Contextual Info: SPI •jri- SP74HCT138 DECODER/DEMULTIPLEXER PIN CONFIGURATION A FEATURES B ■ Designed for high performance memory decoders in microprocessor systems ■ 3 to 8 line decoders include 3 enable inputs ■ Pin com patible with 74LS138 ■ SPI CM OS technology

l381

Abstract: and gate 74LS138 74ls138 function 74LS138 pin for 74LS138 74LS138 pin diagram SP74SC138F SP74SC138N pin diagram demultiplexer 74LS138
Contextual Info: y SP74SC138 DECODER/DEMULTIPLEXER PIN CONFIGURATION A FEATURES B • Designed for high performance memory decoders in microprocessor systems ■ 3 to 8 line decoders include 3 enable inputs ■ Pin com patible with 74LS138 ■ SPI CMOS technology ■ Full TTL interface capability

Contextual Info: GD54/74LS139 DUAL 2-TO-4-LINE DECODERS/DEMULTIPLEXERS Feature Pin Configuration • • Designed Specifically for High Speed Memory Decoders and Data Transmission Systems Schottky Clamped for High Performance Vçç SELECT DATA OUTPUTS ENABLE^_ _

74LS139 pin configuration with

Abstract: 74LS139 74ls139 decoder pin configuration 74ls139 decoder 54LS 74LS
Contextual Info: GD54/74LS139 DUAL 2-TO-4-LINE DECODERS/DEMULTIPLEXERS Feature • • Designed Specifically for High Speed Memory Decoders and Data Transmission Systems Schottky Clamped for High Performance Pin Configuration V çç SELECT DATA OUTPUTS ENABLE^_ _ _

M02S7S7

Contextual Info: GD54/74LS138 3-TO-8-LINE DECODERS/DEMULTIPLEXERS Feature Pin Configuration • Designed Specifically for High Speed Memory Decoders and Data Transmission Systems • Incorporate 3 Enable Inputs to Simplify Cascading AND/OR Data Reception • Schottky Clamped for High Performance

Contextual Info: GD54/74LS138 3-TO-8-LINE DECODERS/DEMULTIPLEXERS Feature Pin Configuration • • • Designed Specifically for High Speed Memory Decoders and Data Transmission Systems Incorporate 3 Enable Inputs to Simplify Cascading AND/OR Data Reception Schottky Clamped for High Performance

Contextual Info: GD54/74LS139 DUAL 2-TO-4-UNE DECODERS/DEMULTIPLEXERS Feature • Designed Specifically for High Speed Memory Decoders and Data Transmission Systems • Schottky Clamped for High Performance Pin Configuration SELECT V çç 25 2A 2B DATA OUTPUTS 2VQ 2V1 2Y2

Contextual Info: MITSUBISHI LSTTLs M 74LS136P QUADRUPLE 2-IN P U T EXCLUSIVE OR GATES W ITH OPEN COLLECTOR OUTPUTS DESCRIPTION The M 74LS 136P containing 4 is a semiconductor integrated circuit dual-input exclusive-OR gates w ith PIN CONFIGURATION TOP VIEW open collector output.

Contextual Info: MITSUBISHI LSTTLs M 74LS137P 3-LINE-TO -8-LINE DECODER/DEMULTIPLEXER W ITH ADDRESS LATCH DESCRIPTION The M 7 4L S 13 7P is a semiconductor integrated circuit con­ PIN CONFIGURATION TOP VIEW taining a 3-line-to-8-line decoder/m ultiplexer function w ith

Contextual Info: GD54/74LS132 QUAD 2-INPUT NAND GATES WITH SCHMITT TRIGGER INPUtS Features Pin Configuration • Suitable for waveforms shaping applications • Wide hysteresis width 0 .8 V typical and high noise margin Vcc 4B 4A 4Y 3B 3A 3Y 1A 1ß 1V 2A 2B 2Y GND Description

M74LS136P

Abstract: 20-PIN MITSUBISHI ELECTRIC SEMICONDUCTOR
Contextual Info: MITSUBISHI LSTTLs M 74LS136P QUADRUPLE 2 -IN P U T EXC LU SIVE OR GATES W IT H OPEN COLLECTOR O UTPU TS DESCRIPTION The M 74LS 136P containing 4 is a semiconductor integrated circuit dual-input exclusive-OR gates w ith PIN CONFIGURATION TOP VIEW open collector output.

working of IC 74ls244 as buffer

Abstract: hdc9234 SMC hdc-9234 HDC9234 SMC A1fe ersa rds 80 bft 5f g1 ibm hard disk drive ana esso
Contextual Info: STANDARD MICROSYSTEMS CORPORATION, HDC 9234 PRELIMINARY Universal Disk Controller PIN CONFIGURATION FEATURES Programmable Disk Drive Interface and Formats □ IBM PC-AT® ST506/412 or user definable hard disk formats □ IBM® PC-AT® compatible ECC algorithm

block diagram of 74LS138 3 to 8 decoder

Abstract: block diagram of 74LS138 1 line to 16 line TTL 74ls138 74LS138 74LS138 3 to 8 74LS138 application note 74LS138 pin configuration 74LS138 3 to 8 decoder Pin of 74LS138 3 to 8 decoder 74ls138 3-8
Contextual Info: GD54/74LS138 3-TO-8-LINE DECODERS/DEMULTIPLEXERS Feature • Pin Configuration • D esigned Specifically for High S p e e d M em ory D ec o d e rs and Data Transm ission System s Incorporate 3 Enable Inputs to Simplify Cascading • A N D /O R Data R eception

M74LS138P

Abstract: M74LSI38P demultiplexer demultiplexer ic 20-PIN pin diagram 14 demultiplexer binary decorder decorder 3 line to 8 line
Contextual Info: DESCRIPTION The M74LS138P is a semiconductor integrated circuit PIN CONFIGURATION TOP VIEW consisting o f a 3-bit binary-octal decoder/dem ultiplexer w ith enable inputs. FEATURES • 3 classes o f enable inputs • 4 to 16 decorder/dem ultiplexer functions are provided

HDC9224

Abstract: HDC9226 FDC9216B HDC 9224 AB704 AB70 floppy disk controller 64 PIN HD
Contextual Info: STANDARD MICROSYSTEMS CORPORATION* HDC 9224 Universal Disk Controller PIN CONFIGURATION FEATU RES Program m able Disk Drive Interface and Formats □ Seagate ST506 or user definable 1 40 3 RDATA Vcc C Hard Disk Formats INT C 2 39 3 EARLY V - Œte « o < ,15 o

M74LS133P

Contextual Info: MITSUBISHI LSTTLs M74LS133P SINGLE 1 3 -IN P U T P O S IT IV E NAND GATE DESCRIPTION The M 7 4L S 13 3P PIN CONFIGURATION TOP VIEW is a semiconductor integrated circuit containing one 13-input positive-logic N A N D gate, usable as a negative logic N O R gate.

Dual 4-input NAND Schmitt Trigger

Abstract: M74LS13P M74ls14p 20-PIN
Contextual Info: MITSUBISHI LSTTLs M74LS13P DUAL 4 -IN P U T NAND S C H M ITT TRIGGER DESCRIPTION The M 74LS 13P PIN CONFIGURATION TOP VIEW is a semiconductor integrated circuit containing tw o 4-inp ut positive-logic N A N D gates having a Schm itt trigger function and negative-logic NOR gates.

Contextual Info: MITSUBISHI LSTTLs M74LS13P DUAL 4 -IN P U T NAND S C H M ITT TRIGGER DESCRIPTION The M 74LS 13P PIN CONFIGURATION TOP VIEW is a semiconductor integrated circuit containing tw o 4-inp ut positive-logic N A N D gates having a Schm itt trigger function and negative-logic NOR gates.

hdc9234

Abstract: ST3800 f 9234 ye data floppy drive ats 667 hdc9 MAGNETIC HEAD impedance UPD4016 5.25 floppy working of IC 74ls244 as buffer
Contextual Info: HDC 9234 STANDARD MICROSYSTEMS CORPORATION PRELIMINARY Universal Disk Controller PIN CONFIGURATION Vcc C sr ! J f c o i t e i i ü in t C RCLK C IÄ 1 0 Q « IŒ Z Û Im û S Œ n n n n n n n n n n n 39 38 37 36 35 34 33 32 31 30 29 CLK C 40 WDATA E 41 LATE C 42

74LS138P

Abstract: M74LS138P 20-PIN pin diagram 14 demultiplexer 3DCX
Contextual Info: DESCRIPTION The M 74LS138P is a consisting o f a 3 -b it s em ico n d u c to r b in a ry -o c ta l in teg rated c irc u it PIN CONFIGURATION TOP VIEW d e c o d e r/d e m u ltip le x e r w ith enable inputs. FEATURES • 3 classes o f enable in puts • 4 t o 1 6 d e c o rd e r/d e m u ltip le x e r fu n c tio n s are provid ed

Dual 4-input NAND Schmitt Trigger

Abstract: M74LS13P M74LS18P M74LS19P 13kT
Contextual Info: MITSUBISHI LSTTLs M74LS18P DUAL 4-IN P U T NAND SCHMITT TRIGGER DESCRIPTION The M 74LS18P is a s e m ico n d u c to r in teg rated c irc u it PIN CONFIGURATION TOP VIEW c o n ta in in g tw o 4 -in p u t po sitive-logic N A N D gates having a s c h m itt trigg er fu n c tio n and negative-logic N O R gates.

74ls137 demultiplexer

Abstract: ic 74ls137 74LS137 4000B M74HC137 M74HC137P
Contextual Info: M IT S U B IS H I HIGH S P E E D C M O S M 74H C 137P l- O F - 8 D E C O D E R /D E M U L T IP L E X E R W IT H A D D R E S S LA T C H DESCRIPTION The M74HC137 is a semiconductor integrated circuit con­ PIN CONFIGURATION TOP VIEW sisting of a 3-bit binary to 8-line decoder/dem ultiplexer with

Contextual Info: M ITSU B ISH I HIGH SPEED CMOS M74HC137P l-O F -8 D E C O D E R /D E M U L T IP L E X E R W ITH ADDRESS LATCH DESCRIPTION The M 74H C 137 is a sem iconductor inte grated circu it con­ PIN CONFIGURATION TOP VIEW sisting of a 3 -b it binary to 8-lin e d e c o d e r/d e m u ltip le x e r with

VT10L

Contextual Info: M ITSU B ISH I HIGH SPEED CMOS M 74H C 132P /FP /D P QUADRUPLE 2 -IN P U T S C H M IT T -T R IG G E R P O S IT IV E NAND GATE DESCRIPTION T h e M 7 4 H C 1 3 2 is a sem iconductor in teg rated circuit con­ PIN CONFIGURATION TOP VIEW sisting of four 2-inp ut S ch m itt-trig g er positive-logic N A N D