PECL TERMINATOR Search Results

ST 9340

Contextual Info: DISCRETE SEMICONDUCTORS DATA SHEET ge M3D088 PSSI3120CA PECL termination Product specification 2001 Jul 19 Philips Semiconductors Product specification PECL termination PSSI3120CA PINNING - SOT23 FEATURES • Single channel PECL termination in a three pin SOT23

Contextual Info: Positive Emitter Coupled Logic PECL Chip Terminator RN Series * 1.0 Application This surface mount chip resistor network is for the termination of Positive Emitter Coupled Logic (PECL) circuits and CCITT 3.5v termination. The Susumu World Group provides off the shelf chip

Emitter Coupled Logic

Abstract: R15-0
Contextual Info: Positive Emitter Coupled Logic PECL Chip Terminator RN Series 1.0 Description This surface mount chip resistor network is for the termination of Positive Emitter Coupled Logic (PECL) circuits and CCITT 3.5v termination. The Susumu World Group provides off the shelf chip

Contextual Info: Positive Emitter Coupled Logic PECL Chip Terminator RN Series 1.0 Application This surface mount chip resistor network is for the termination of Positive Emitter Coupled Logic (PECL) circuits and CCITT 3.5v termination. The Susumu World Group provides off the shelf chip

TP05

Abstract: TF18 0.2 ohm 5W emitter resistor 1000H TP30 15W 50 Ohm Resistors tp-05 TF28A TP125
Contextual Info: CHIP TERMINATOR NETWORK – PECL, Fixed, & Power The content of this specification may change without notification 11/18/05 Custom solutions are available. PECL Chip Terminator HOW TO ORDER T X 1206 50 F M Packaging M = tape/reel 5,000 pcs O = tape/reel 1,000 pcs

Contextual Info: CHIP TERMINATOR NETWORK – PECL, Fixed, & Power Custom solutions are available. PECL Chip Terminator HOW TO ORDER T X 1206 50 F M Packaging M = tape/reel 5,000 pcs O = tape/reel 1,000 pcs Tolerance % F= +1% Blank for TF or TP Series Impedance 50Ω or 75Ω

PRL-ACT-50

Abstract: PRL-460ANPD
Contextual Info: PRL-460ANPD DUAL CHANNEL NECL TO PECL TRANSLATOR PRL-460ANLPD DUAL CHANNEL NECL TO LVPECL TRANSLATOR APPLICATIONS o o o Converting Single Ended or Differential NECL Signals to Differential PECL or LVPECL Signals High Speed Digital Communications systems Testing

HP-54121A

Abstract: HP54121A feedthru cap DC-10 pecl logic voltage levels
Contextual Info: Model 5620 Series ECL and PECL Terminators Signals from ECL logic ICs are specified to be terminated into 50 Ω returned to Vcc - 2V. Most test instrumentation, including high bandwidth digital sampling oscilloscopes have input impedances of 50 Ω to ground. Historically, this has caused problems for measuring ECL or PECL signals. The Model 5620

HP53132A

Abstract: PCC2147CT-ND P130H TTC 104 SY87700L SY87700V SY87701L HP-15 hp 70841 8133A LED
Contextual Info: SY87700/SY87701 CDR EVALUATION KIT FEATURES SY87700/SY87701 EVALUATION BOARD DESCRIPTION • 3.3V power supply: Split VCC = +2V, GND = 0V VEE = –1.3V for 3.3V VEE = –3V for 5.0V ■ Simple switch configuration ■ PECL signal outputs ■ Simple RDIN+, RDIN– PECL inputs

Contextual Info: « 01/Iie n /« V LOW-POWER HEX PECL-TO-TTL TRANSLATOR SYNERGY SEMICONDUCTOR FEATURES PRELIMINARY SY100S390 DESCRIPTION The SY100S390 is a hex PECL-to-TTL translator for converting 100K logic levels to TTL logic levels. Unlike other level translators, the SY100S390 operates using only one

100391PC

Abstract: 100391QC 100391QI 100391SC F100K M24B MO-047 MS-011 MS-013 N24E
Contextual Info: Revised November 1999 100391 Low Power Single Supply Hex TTL-to-PECL Translator General Description Features The 100391 is a hex translator for converting TTL logic levels to F100K PECL logic levels. The unique feature of this translator, is the ability to do this translation using only one

F100K

Abstract: SY100S391 SY100S391FC SY100S391JC SY100S391JCTR
Contextual Info: LOW-POWER HEX TTL-TO-PECL TRANSLATOR FEATURES DESCRIPTION The SY100S391 is a hex TTL-to-PECL translator for converting TTL logic levels to 100K logic levels. The unique feature of this translator is the ability to do this translation using only one +5V supply. The differential outputs allow

Contextual Info: LOW-POWER HEX TTL-TO-PECL TRANSLATOR FEATURES DESCRIPTION The SY100S391 is a hex TTL-to-PECL translator for converting TTL logic levels to 100K logic levels. The unique feature of this translator is the ability to do this translation using only one +5V supply. The differential outputs allow

Contextual Info: LOW-POWER HEX TTL-TO-PECL TRANSLATOR Micrel, Inc. FEATURES • ■ ■ ■ SY100S391 SY100S391 DESCRIPTION The SY100S391 is a hex TTL-to-PECL translator for converting TTL logic levels to 100K logic levels. The unique feature of this translator is the ability to do this translation

100391PC

Abstract: 100391QC 100391QI 100391SC F100K M24B MO-047 MS-013 N24E V28A
Contextual Info: Revised August 2000 100391 Low Power Single Supply Hex TTL-to-PECL Translator General Description Features The 100391 is a hex translator for converting TTL logic levels to F100K PECL logic levels. The unique feature of this translator, is the ability to do this translation using only one

F100K

Abstract: SY100S391 SY100S391JC SY100S391JCTR
Contextual Info: LOW-POWER HEX TTL-TO-PECL TRANSLATOR Micrel, Inc. FEATURES • ■ ■ ■ SY100S391 SY100S391 DESCRIPTION The SY100S391 is a hex TTL-to-PECL translator for converting TTL logic levels to 100K logic levels. The unique feature of this translator is the ability to do this translation

Contextual Info: LOW-POWER HEX TTL-TO-PECL TRANSLATOR Micrel, Inc. FEATURES • ■ ■ ■ SY100S391 SY100S391 DESCRIPTION The SY100S391 is a hex TTL-to-PECL translator for converting TTL logic levels to 100K logic levels. The unique feature of this translator is the ability to do this translation

Contextual Info: s e m ic o n d u c t o r Revised November 1999 100391 Low Power Single Supply Hex TTL-to-PECL Translator General Description Features The 100391 is a hex translator for converting TTL logic lev­ els to F100K PECL logic levels. The unique feature of this

Parallel Interfaces

Abstract: demux ic lvds MUX/DEMUX MAX3880 MAX3881 MAX3890 MAX3891
Contextual Info: FIBER INNOVATIONS FROM MAXIM 2.5Gbps OC-48 TRANSCEIVER CHIPSETS FOR LVDS OR PECL PARALLEL INTERFACES Low-Power 3.3V Mux and Demux + CDR Exceed Jitter Specs Maxim’s 16:1/1:16 mux/demux chipsets give users the option of LVDS or single-ended PECL parallel interfaces. Their small form-factor, low power consumption, and excellent jitter performance make both the

Contextual Info: Positive Emitter Coupled Logic PECL Chip Terminators Suitable for output applications in emitter coupled logic for high-speed signal transmission. Minimized reflection permits high-speed data processing. Completely lead free RoHS compliant SPECIFICATIONS

Contextual Info: Positive Emitter Coupled Logic PECL Chip Terminators Suitable for output applications in emitter coupled logic for high-speed signal transmission. Minimized reflection permits high-speed data processing. Completely lead free RoHS compliant SPECIFICATIONS

Emitter Coupled Logic

Abstract: RN1632F
Contextual Info: Positive Emitter Coupled Logic PECL Chip Terminators Suitable for output applications in emitter coupled logic for high-speed signal transmission. Minimized reflection permits high-speed data processing. Completely lead free RoHS compliant SPECIFICATIONS

Contextual Info: Positive Emitter Coupled Logic PECL Chip Terminators Suitable for output applications in emitter coupled logic for high-speed signal transmission. Minimized reflection permits high-speed data processing. SPECIFICATIONS 0.4Ϯ0.1 3.2Ϯ0.2 Mechanical 1.0Ϯ0.25

Emitter Coupled Logic

Abstract: R15-0
Contextual Info: Positive Emitter Coupled Logic PECL Chip Terminators Suitable for output applications in emitter coupled logic for high-speed signal transmission. Minimized reflection permits high-speed data processing. SPECIFICATIONS 0.4Ϯ0.1 3.2Ϯ0.2 Mechanical 1.0Ϯ0.25