PECL LOGIC VOLTAGE LEVELS Search Results

m2071

Abstract: M2054 M2057 m2061 M2063 "Voltage Controlled Oscillators" M2051
Contextual Info: FULL SIZE D.I.L. M2051 thru M2057 L2051 thru L2057 M2061 thru M2063 L2061 thru L2063 M2071 thru M2073 L2071 thru L2073 VOLTAGE CONTROLLED OSCILLATORS 10KH PECL Logic, 0° to 70°C Thru-Hole, 5V 1 MHz to 175 MHz PECL 10KH – Thru-Hole VCXOs, 5V These thru-hole VCXOs are designed for

Contextual Info: MAX3822 I/O Model SPICE I/O Macromodels aid in understanding signal integrity issues in electronic systems. Most of Maxim’s High Frequency/Fiber Communication ICs utilize input and output I/O circuits with Current Mode Logic (CML), Positive Emitter Coupled Logic (PECL), and Low Voltage Differential Signal (LVDS)

F100K

Abstract: SY100S391 SY100S391FC SY100S391JC SY100S391JCTR
Contextual Info: LOW-POWER HEX TTL-TO-PECL TRANSLATOR FEATURES DESCRIPTION The SY100S391 is a hex TTL-to-PECL translator for converting TTL logic levels to 100K logic levels. The unique feature of this translator is the ability to do this translation using only one +5V supply. The differential outputs allow

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA TTL to Differential PECL Translator MC10ELT20 MC100ELT20 The MC1OELT/100ELT20 is a TTL to differential PECL translator. Because PECL Positive ECL levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the single gate of

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual TTL to Differential PECL Translator MC10ELT22 MC100ELT22 The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL Positive ECL levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the low skew, dual

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual Differential PECL to TTL Translator MC100ELT23 The MC100ELT23 is a dual differential PECL to TTL translator. Because PECL Positive ECL levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the dual gate

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Differential PECL to TTL Translator MC10ELT21 MC100ELT21 The MC10ELT/100ELT21 is a differential PECL to TTL translator. Because PECL Positive ECL levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the single gate of

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual D ifferential PECL to TTL Translator M C100ELT23 The MC100ELT23 is a dual differential PECL to TTL translator. Because PECL Positive ECL levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the dual gate

Contextual Info: LOW-POWER HEX TTL-TO-PECL TRANSLATOR Micrel, Inc. FEATURES • ■ ■ ■ SY100S391 SY100S391 DESCRIPTION The SY100S391 is a hex TTL-to-PECL translator for converting TTL logic levels to 100K logic levels. The unique feature of this translator is the ability to do this translation

Contextual Info: M OTOROLA SEMICONDUCTOR TECHNICAL DATA Differential PECL to TTL Translator MC10ELT21 MC100ELT21 The MC10ELT/100ELT21 is a differential PECL to TTL translator. Because PECL Positive ECL levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the single gate of

7252 motorola

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Differential PECL to TTL Translator MC10ELT21 MC100ELT21 The MC10ELT/100ELT21 is a differential PECL to TTL translator. Because PECL Positive ECL levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the single gate of the

Contextual Info: M OTOROLA SEMICONDUCTOR TECHNICAL DATA TTL to Differential PECL Translator MC10ELT20 MC100ELT20 The MC10ELT/100ELT20 is a TTL to differential PECL translator. Because PECL Positive ECL levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the single gate of

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual TTL to Differential PECL Translator MC10ELT22 MC100ELT22 The MC10ELT/100ELT22 is a dual T T L to differential PECL translator. Because PEC L Positive ECL levels are used only +5V and ground are required. The sm all outline 8-lead SOIC package and the low skew, dual

Contextual Info: ClockWorks SY10ELT21 ClockWorks™ SY100ELT21 DIFFERENTIAL PECL-to-TTL TRANSLATOR SYNERGY SY10ELT21 SY100ELT21 SEMICONDUCTOR FEATURES • ■ ■ ■ ■ ■ ■ DESCRIPTION The SY10/100ELT21 are single differential PECL-toTTL translators. Because PECL Positive ECL levels are

Contextual Info: V SYNERGY DUA LTTL-tO -DIFFERENTIAL PECL TRANSLATOR SY10ELT22 SY100ELT22 S E M IC O N D U C T O R DESCRIPTION FEATURES 300ps typical propagation delay The S Y 10/100ELT22 are dual T TL-to-differential PECL translators. Because PECL P ositive ECL levels are

8-pin 3773

Abstract: 100ELT21 3773
Contextual Info: SK10/100ELT21W Differential PECL to CMOS/TTL Translator PRELIMINARY HIGH-PERFORMANCE PRODUCTS Description Features The SK10/100ELT21W is a single differential PECL to CMOS/TTL Translator. Since PECL Positive ECL levels are used, only +VCC and ground are required.

100391PC

Abstract: 100391QC 100391QI 100391SC F100K M24B MO-047 MS-011 MS-013 N24E
Contextual Info: Revised November 1999 100391 Low Power Single Supply Hex TTL-to-PECL Translator General Description Features The 100391 is a hex translator for converting TTL logic levels to F100K PECL logic levels. The unique feature of this translator, is the ability to do this translation using only one

KLT28

Abstract: HLT28 HT28 KT28 MC100ELT28 MC10ELT28 transistor k 4110
Contextual Info: MC10ELT28, MC100ELT28 5V TTL to Differential PECL and Differential PECL to TTL Translator The MC10ELT/100ELT28 is a differential PECL to TTL translator and a TTL to differential PECL translator in a single package. Because PECL Positive ECL levels are used, only +5 V and ground are

FC940L

Abstract: FC940LVB MPC940L
Contextual Info: Revised January 1999 FC940L Low Voltage 1 to 18 Clock Distribution Device with Selectable PECL or LVTTL Input General Description Features The FC940L is a 1 to 18 low voltage clock fanout buffer. The device allows for the selection of either differential PECL or LVTTL/CMOS input levels. The 18 outputs are

VFXO311

Contextual Info: VFXO311 XO Ultra Low Jitter 2.5V, 3.3V 5x7mm SMD, LVPECL / LVDS / LVCMOS Features      RoHS Status 60MHz to 320MHz frequency range Differential output levels LVPECL/LVDS Single ended LVCMOS output available <0.2ps RMS jitter over 12kHz to 20MHz

Contextual Info: VFXO321 XO Ultra Low Jitter 2.5V, 3.3V 5x7mm SMD, LVPECL / LVDS / LVCMOS Features      RoHS Status 16MHz to 800MHz frequency range Differential output levels LVPECL/LVDS Single ended LVCMOS output available <0.2ps RMS jitter over 12kHz to 20MHz

Contextual Info: VFVX321 VCXO Ultra Low Jitter 2.5V, 3.3V 5x7mm SMD, LVPECL / LVDS / LVCMOS Features      RoHS Status 60MHz to 800MHz* frequency range Differential output levels LVPECL/LVDS Single ended LVCMOS output available <0.2ps RMS jitter over 12kHz to 20MHz

Contextual Info: DUAL DIFFERENTIAL SYNERGY PECL-tO-TTL TRANSLATOR sy10J | l t 2 3 SEMICONDUCTOR DESCRIPTION FEATURES 3.0ns typical propagation delay The SY 10/100ELT23 are dual differential PE C L-to-TTL translators. Because PECL Positive ECL levels are used, only +5V and ground are required. The sm all

klt22

Abstract: HLT22 ELT22 HT22 MC100 MC100ELT22 MC10ELT22
Contextual Info: MC10ELT22, MC100ELT22 5V Dual TTL to Differential PECL Translator The MC10ELT/100ELT22 is a dual TTL to differential PECL translator. Because PECL Positive ECL levels are used only +5 V and ground are required. The small outline 8-lead package and the low