IR 30 D1
Abstract: No abstract text available
Text: SN74ALS236 64 x 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SDAS107A-OCTOBER 1986 - REVISED SEPTEMBER 1993 Asynchronous Operation Organized as 64 Words by 4 Bits DW OR N PACKAGE TOP VIEW r NC [ 1 Data Rates From 0 to 30 MHz 3-State Outputs 16 J VCC 15 ] S O
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SN74ALS236
SDAS107A-OCTOBER
300-mll
256-bit
IR 30 D1
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tr8c
Abstract: TMS28F200
Text: TMS28F20ÛBZT, TMS28F200BZB 262144 BY 8-BIT/131072 BY 16-BIT BOOT-BLOCK FLASH MEMORIES SWS2dOO - JUNE 1 9 9 4 - REVISED SEPTEMBER 1997 • ■ I I I • • • • • • • • • • Organization . . . 262144 by 8 bits 131072 by 16 bits Array-Blocking Architecture
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TMS28F20
TMS28F200BZB
8-BIT/131072
16-BIT
96K-Byte
128K-Byte
16K-Byte
28F200B2x70
28F200BZX80
28F200BZX90
tr8c
TMS28F200
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Untitled
Abstract: No abstract text available
Text: TOSHIBA TC55V2325FF-100 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 65,536 W O R D x 32 BIT Synchronous Pipelined Burst SRAM DESCRIPTION The TC55V2325FF is a 2 ,0 9 7 ,1 5 2 bit synchronous pipelined burst SRAM that is organized as 65,536 words by 32 bits and designed for use in a secondary cache to support MPUs which have burst
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TC55V2325FF-100
TC55V2325FF
64KX32
LQFP100-P-1420-0
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Untitled
Abstract: No abstract text available
Text: TMS28C64 65,536-BIT ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY • Organization 8K x 8 • Single 5-V Power Supply ± 10% N AND J PACKAGES (TOP VIEW } Q 1 U A 12C 2 A7C 3 Compatible with Existing 64K M O S EPRO M s. PRO M s. R O M s, and EEPR O M s
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TMS28C64
536-BIT
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Untitled
Abstract: No abstract text available
Text: TC55417P/J —15H. TC55417P/J-20H TC55417P/J—25H. TC55417P/J-35H • * 16,384 W O R D x 4 BIT CMOS STATIC RAM DESCRIPTION The TC55417P/J—H is a 65,536 bit high speed static random access memory organized as 16,384 words by 4 bits using CMOS technology, and operated from a single 5 - volt supply.
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TC55417P/J
--15H.
TC55417P/J-20H
TC55417P/J--25H.
TC55417P/J-35H
TC55417P/J--
120mA
100mA
TC55417P/J--H
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TMS4116
Abstract: TMS4132
Text: MOS LSI TMS 4132 JDL 32,768-BIT DYNAMIC RANDOM-ACCESS MEMORY NOVEMBER 1979 32,768 «AX SUPPLY 1 X 1 Organization 10% Tolerance on All Supplies • All Inputs Including Clocks TTL-Compatible
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768-BIT
18-PIN
200ACCESS
4132JD
TMS4116
TMS4132
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ic tl 741
Abstract: S47C256
Text: AD V A N C E INFORM ATION TM S47C256 32,768-W ORD BY 8-BIT R EAD -O N LY M EM O R Y NOVEM BER 1 9 8 5 3 2 ,7 6 8 X 8 Organization N PACKAGE TOP VIEW Fully Static (No Clocks. No Refresh) NC C 1 y j 2 Q : 27 : A12 C 2 A7 C 3 26 : All Inputs and Outputs TTL Compatible
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S47C256
256-1S
ic tl 741
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A9RV
Abstract: 5s a315 A327
Text: TOSHIBA TC514900AJLL-70/80 524,288 WORD X 9 BIT DYNAMIC RAM DESCRIPTION The TC514900AJLL is the new generation dynamic RAM organized 524,288 word by 9 bit. The TC514900AJLL utilizes Toshiba’s CMOS silicon gate process technology as well as advanced circuit
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TC514900AJLL-70/80
TC514900AJLL
TC514900AJLI/70/80
TC514900AJLL70/80
A9RV
5s a315
A327
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PDF
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74ALS234
Abstract: No abstract text available
Text: SN54ALS234, SN74ALS234 64 x 4 ASYNCHRONOUS FIRST-IN FIRST OUT MEMORY 0 2 9 5 8 , OCTOBER 1 9 8 6 Asynchronous Operation S N 54A LS 234 . . . J PACKAGE S N 74A LS 234 . . . 0 OR N PACKAGE Organized as 6 4 Words of 4 Bits Management Products TOP VIEW! Data Rates from 0 to 30 MHz
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SN54ALS234,
SN74ALS234
I67401B
256-bit
192-WORD
12-BIT
74ALS234
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tms4256
Abstract: TMS4266
Text: INSTR TM4256EL9, TM4256GU9 262,144 BY 9-BIT DYNAMIC BAM MODULES 7“-ifc-23-/7 25E D SEPTEMBER 1986 — REVISED M ARCH 1968 A SIC /MEMORY 262,144 x 9 Organization TM4266EL9 . . . L SMQLE-IN-UNE PACKAGE (TOP VIEWl_ Slngla 5-V Supply (10% Tolerance)
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U17ES
077GC
TM4256EL9,
TM4256GU9
-ifc-23-/7
TM4266EL9
30-Pln
TM4256EL9)
TM4266GU9)
tms4256
TMS4266
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PDF
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NCC equivalent
Abstract: No abstract text available
Text: TMS29F400T, TMS29F400B 524288 BY 8-BIT/262144 BY 16-BIT FLASH M EMORIES • I • Single Power Supply Supports 5 V ± 10% Read/Write Operation I I • Organization . . . I • Array-Blocking Architecture - One 16K-Byte/One 8K-Word Boot Sector - Two 8K-Byte/4K-Word Parameter Sectors
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TMS29F400T,
TMS29F400B
8-BIT/262144
16-BIT
SMJS843A
44-Pin
48-Pin
8-Blf/262144
NCC equivalent
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PDF
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th50vsf1400
Abstract: BA30
Text: TOSHIBA TH 50VSF1400/1401ACXB TENTATIVE TOSHIBA MULTI CHIP INTEGRATED CIRCUIT SILICON GATE CMOS SRAM A N D FLASH M E M O R Y M IX E D M U LTI-C H IP PACKAGE DESCRIPTION The TH50VSF1400/1401ACXB is a mixed containing a package 2,097,152-bit SRAM and a 16,777,216-bit flash memory. The SRAM is organized as 262,144 words by 8 bits and the flash memory
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50VSF1400/1401ACXB
TH50VSF1400/1401ACXB
152-bit
216-bit
48-pin
50VSF1400/1401
th50vsf1400
BA30
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PDF
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A1051
Abstract: No abstract text available
Text: TMS27C291, TMS27C292 16.384-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORIES TMS27PC291 16,384-BIT PROGRAMMABLE READ-ONLY MEMORY SEPTEM BER 1986 —REVISED APRIL 1988 Organization . . . 2K x 8 J AND N PA C KA G E Pin Compatible with Existing 2K x 8 Bipolar/High-Speed CM OS EPROMs
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TMS27C291,
TMS27C292
384-BIT
TMS27PC291
27C/PC291-3
27C/PC291
27C/PC291-5
27C/PC291-35
27C/PC291-45
A1051
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PDF
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27C020-12
Abstract: 27PC020-12 LS020 A1025 LS020B 2097152-BIT
Text: TMS27C020 2097152-BIT UV ERASABLE PROGRAMMABLE TMS27PC020 2097152-BIT PROGRAMMABLE READ-ONLY MEMORY SM LS020B - N O V E M B E R 1990 - REVISED JU N E 1995 • Organization . . . 256K x 8 J PACKAGE TOP VIEW • Single 5-V Power Supply • Operationally Compatible With Existing
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TMS27C020
2097152-BIT
TMS27PC020
LS020B
32-Pln
32-Lead
27C/PC020-12
27C/PC020-15
27C/PC020-20
27C020-12
27PC020-12
LS020
A1025
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Untitled
Abstract: No abstract text available
Text: TOSHIBA TC58V64FT/DC TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 64-MBIT 8M X 8 BITS CMOS NAND E2PROM DESCRIPTION The TC58V64FT/DC is a single 3.3-V 64-Mbit (69,206,016-bit) NAND electrically erasable and programmable read-only memory (NAND E2PROM) organized as 528 bytes X 16 pages X 1024 blocks.
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TC58V64FT/DC
64-MBIT
TC58V64FT/DC
016-bit)
528-byte
44/40-P-400-0
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4A04I
Abstract: tc514100a
Text: TC51441OAP/AJ/ASJ/AZ—70, TC51441OAP/AJ/ASJ/AZ-80 TC51441OAP/AJ/ASJ/AZ-10 PRELIMINARY 1,048,576 W ORD x 4 BIT DYNAMIC RAM DESCRIPTION The TC51441 OAP/AJ/ASJ/AZ is the new generation dynamic RAM organized 1,048,576 words by 4 bits. The TC514410AP/AJ/ASJ/AZ utilizes TOSHIBA’S CMOS Silicon gate process technology as well as
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TC51441OAP/AJ/ASJ/AZ--
TC51441OAP/AJ/ASJ/AZ-80
TC51441OAP/AJ/ASJ/AZ-10
TC51441
TC514410AP/AJ/ASJ/AZ
350mil)
TC514100AP/AJ/ASJ/AZ.
TC5141OOAP/AJ/ASJ/AZ-60
4A04I
tc514100a
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Untitled
Abstract: No abstract text available
Text: • ■ ! ■ ■ ■ ■ • '|<f TOSHIBA MIOS MEMORY PRODUCTS 8,192 WORD X 8 BIT CM OS STATIC RAM SILICON GATE C M O S T C 5 5 63 A P L-1 0, T C 5563A P L-12 T C 55 6 3 A P L -1 5 DESCRIPTIO N The TC5563APL is 65,536 bit static random access memory organized as 8,1 92 words by 8 bits
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TC5563APL
TMM2764D)
6D28A-P)
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PDF
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BE423
Abstract: No abstract text available
Text: TOSHIBA TC5118325BJ/BFT-70 PRELIMINARY 524,288 WORD X 32 BIT EDO DYNAMIC RAM Description The TC5118325BJ/BFT is the Hyper Page Mode (EDO) dynamic RAM organized 524,288 words by 32 bits. The TC5118325BJ/BFT utilizes Toshiba’s CMOS silicon gate process technology as well as advanced circuit techniques to pro
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TC5118325BJ/BFT-70
TC5118325BJ/BFT
TC5118325BJ/
400mil)
I/024
I/025
I/032
BE423
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PDF
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TC514170BJ-80
Abstract: tc514170 TC514170BJ80
Text: TOSHIBA TC514170BJ-70/80 262,144 WORD X 16 BIT DYNAMIC RAM DESCRIPTION The TC514170BJ is the new generation dynam ic RAM organized 262,144 word by 16 bit. The TC514170BJ utilizes T oshiba’s CM OS silicon gate process technology as well as advanced circuit techniques
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TC514170BJ-70/80
TC514170BJ
TC514170BJ-80
tc514170
TC514170BJ80
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PDF
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Untitled
Abstract: No abstract text available
Text: TM4164EC4 65,536 BY 4-BIT DYNAMIC RAM MODULE NOVEMBER 1983 - REVISED NOVEMBER 1985 SINGLE-IN-UNE PACKAGE 6 5 ,5 3 6 X 4 Organization TOP VIEW Single 5-V Supply (10% Tolerance) 22-Pin Single-in-Line Package (SIP) Utilizes Four 64K Dynamic RAMs in Plastic
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TM4164EC4
22-Pin
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PDF
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TC5117445CSJ
Abstract: No abstract text available
Text: TO SHIBA_ TC5117445CSJ-40,-50,-60 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 4,194,304-WORD BY 4-BIT EDO HYPER PAGE DYNAMIC RAM DESCRIPTION The TC5117445CSJ is an EDO (Hyper Page) dynamic RAM organized as 4,194,304 words by 4 bits. The
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OCR Scan
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TC5117445CSJ-40
304-WORD
TC5117445CSJ
28-pin
17445CSJ-40
TC5117445CSJ
SOJ28
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PDF
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TC5316200bP
Abstract: TC5316200BP/BF
Text: TOSHIBA TC5316200BP/BF SILICON STACKED GATE CMOS 1,048,576 WORD x 16 BIT/2,097,152 WORD x 8 BIT CMOS MASK ROM D escription The TC5316200BP/BF is a 16,777,216 bit read only memory organized as 1,048,576 words by 16 bits when BY I t is logical high, and organized as 2,097,152 words by 8 bits when BYTE is logical low.
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TC5316200BP/BF
TC5316200BP/BF
600mil
42-pin
44-pin
TC5316200BP
TC5316200BF
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PDF
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44c256
Abstract: 3034C
Text: SMJ44C256 262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY _ SGMS034C - MAY 1989 - B E V ILO JUNE 1965 Organization. . . 262144 Words x 4 Bits Single 5-V Supply 10% Tolerance Processed to MIL-STD-833, Class B Performance Ranges: 3-State Unlatched Output
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SMJ44C256
SGMS034C
MIL-STD-833,
SMJ44C256-80
SMJ44C256-10
SMJ44C256-12
SMJ44C256-15
20-Pin
300-Mil
20-Lead
44c256
3034C
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PDF
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TC51V18160
Abstract: No abstract text available
Text: INTEGRATED TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT CIRCUIT TC51V18160 C S / CFTS - 60 TOSHIBA TECHNICAL DATA SILICON GATE CMOS TENTATIVE DATA 1,048,576 WORD x16 BIT FAST PAGE DYNAMIC RAM DESCRIPTION The TC51V1S160CJS-CFTS is the fast page dynamic R A M organized 1,048,576 words by 16 bits.
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TC51V18160
TC51V1S160CJS-CFTS
TC51V18160CJS
TC51V18160CJS/CFTS
73MAX
TSOP50-P-400)
875TYP
35MAX
TC51V18160CJS/CFT>
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PDF
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