Untitled
Abstract: No abstract text available
Text: 54AC11109, 74AC11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET TI0066— D2957, M ARCH 1987— REVISED M ARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11109 . . . J PACKAGE 74AC11109 . . . D OR N PACKAGE TOP VIEW
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54AC11109,
74AC11109
TI0066--
D2957,
500-mA
STD-883C
300-mil
54AC11109
74AC11109
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PDF
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IGBT loss calculate
Abstract: No abstract text available
Text: n j] DN-57 b U N IT R O D E Design Note Power Dissipation Considerations for the UC3726N/UC3727N IGBT Driver Pair by Mickey McClure Application Engineer Motion Control Products Optimized or driving Insulated Gate Bipolar Transis tors (IGBTs , the UC3726N/UC3727N IGBT driver
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DN-57
UC3726N/UC3727N
UC3726N
UC3727N
UC3726/UC3727
U-143C)
U-143C.
15kHz
UC3726N,
IGBT loss calculate
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PDF
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Untitled
Abstract: No abstract text available
Text: 54AC11032, 74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES TI0060— D2957, JULY 1987— REVISED MARCH 1990 54A C 11032 . . . J PACKAGE 74A C 11032 . . . D OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout TOP VIEW • Center-Pin V c c and GND Configurations to
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OCR Scan
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54AC11032,
74AC11032
TI0060--
D2957,
500-mA
300-mil
54AC11032
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PDF
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Untitled
Abstract: No abstract text available
Text: 54AC11021,74AC11021 DUAL 4-INPUT POSITIVE-AND GATES _ D2957. JULY 1987 - REVISED APRIL 1993 54AC11021 . . . J PACKAGE 74AC11021 . . . D OR N PACKAGE TOP VIEW * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations
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OCR Scan
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54AC11021
74AC11021
D2957.
500-mA
300-mll
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PDF
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Untitled
Abstract: No abstract text available
Text: 54AC11002, 74AC11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES D2957, JUNE 1987 - REVISED APRIL 1993 54AC11002 . . . J PACKAGE 74AC11002 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin Vcc and GND Configuration Minimizes High-Speed Switching Noise
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OCR Scan
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54AC11002,
74AC11002
D2957,
500-mA
300-mil
54AC11002
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PDF
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Untitled
Abstract: No abstract text available
Text: 54ACT11002,74ACT11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCAS003A - D2957, JUNE 1987 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-PIn V^c and GND Configurations Minimize High-Speed Switching Noise
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OCR Scan
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54ACT11002
74ACT11002
SCAS003A
D2957,
500-mA
300-mll
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PDF
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D2957
Abstract: No abstract text available
Text: 54AC11241, 74AC11241 OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS I_ • ■ I I I D2957, JULY 1987-R E V IS E D APRIL 1993 * 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations
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OCR Scan
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500-mA
300-mll
AC11240
AC11244,
D2957
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PDF
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74AC11520
Abstract: No abstract text available
Text: 54AC11520,74AC11520 8-BIT IDENTITY COMPARATORS D2957, JULY 1987 - REVISED APRIL 1993 54AC11520 . . . J PACKAGE 74AC11S20. . . DW OR N PACKAGE TOP VIEW Compares TVvo 8-Bit Words Flow-Through Architecture Optimizes PCB Layout Center-PIn Vcc and GND Configurations
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OCR Scan
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54AC11520
74AC11520
D2957,
500-mA
300-mil
54AC11520
74AC11S20.
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PDF
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2a117
Abstract: No abstract text available
Text: 54AC11158, 74AC11158 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS TI010&— D 2957 JULY 1969— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11158 . . . J PACKAGE 74AC11158 . . . DW OR N PACKAGE TOP VIEW Center-Pin V c c and GND Configurations to
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OCR Scan
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54AC11158,
74AC11158
TI010
500-mA
300-mil
54AC11158
74AC11158
2a117
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PDF
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Pulse Width Modulator
Abstract: UC1573
Text: UC1573 UC2573 UC3573 H IN T E G R A T E D C IR C U IT S UNITRQDE Buck Pulse Width Modulator Stepdown Voltage Regulator ADVANCED INFORMATION FEATURES DESCRIPTION • The UC1573 is a Buck pulse width modulator which steps down and regu lates a positive input voltage. The chip is optimized for use in a single
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UC1573
UC2573
UC3573
UPG-94107
UC3573
12VTO
UDG-94106
Pulse Width Modulator
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PDF
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TC5117405
Abstract: No abstract text available
Text: TOSHIBA THM328025BS/BS&60/70 PRELIMINARY 8,388,608 WORDS X 32 BIT EDO DYNAMIC RAM MODULE Description The THM328025BS/BSG is a 8,388,608 words by 32 bits Hyper Page Mode (EDO) dynamic RAM module which assembled 16 pcs of TC5117405BSJ on the printed circuit board. This module is optimized for application to the systems which are
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THM328025BS/BS
THM328025BS/BSG
TC5117405BSJ
704mW
THMxxxxxx-60)
074mW
THMxxxxxx-70)
DM32020695
M328025BS/BSG
THM328025BS/BSG-6Q/70
TC5117405
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PDF
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D3348
Abstract: 74AC11151
Text: 74AC11151 1-0F-8 DATA SELECTOR/MULTIPLEXER D3348, JUNE 1989 - REVISED APRIL 1993 * 8-Llne to 1-Llne Multiplexers Can Perform as Boolean Function Generators, Parallel-to-Serlal Converters, or Data Source Selectors * Flow-Through Architecture Optimizes PCB Layout
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OCR Scan
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74AC11151
D3348,
500-mA
300-mil
D3348
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PDF
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120v battery charger Schematic Diagram
Abstract: schematic diagram 48V battery charger regulator schematic diagram 48V automatic battery charger battery charger schematic 24V
Text: y UNITRODE Advanced Low Voltage Boost Controller With Backup Charger UCC29401 UCC39401 ADVANCE INFORMATION FEATURES DESCRIPTION • Synchronous Conversion with Internal MOSFETs The UCC39401 is a multi-output single inductor synchronous boost control ler optimized to operate from a low input voltage such as a single or dual
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200mW
UCC29401
UCC39401
UCC39401
120v battery charger Schematic Diagram
schematic diagram 48V battery charger regulator
schematic diagram 48V automatic battery charger
battery charger schematic 24V
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PDF
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Untitled
Abstract: No abstract text available
Text: 54AC 11004, 74AC11004 HEX INVERTERS TI0044— D2957, FEBRUARY 1068— REVISED M ARCH 1990 54AC11004 . . . J PACKAGE 74AC11004 . . . DW OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout TOP VIEW • Center-Pin Vq c and GND Configurations to
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OCR Scan
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74AC11004
TI0044--
D2957,
500-mA
300-mil
54AC11004
74AC11004
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PDF
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54AC11181
Abstract: TI018
Text: 54AC11181, 74AC11181 ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS T I0184— D 3119, APRIL 1989— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11181 . . . JT PACKAGE 74AC11181 . . . DW OR NT PACKAGE TOP VIEW Minimize High-Speed Switching Noise
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OCR Scan
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54AC11181,
74AC11181
I0184--
500-mA
300-mil
54AC11181
74AC11181
54AC11181
TI018
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PDF
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Untitled
Abstract: No abstract text available
Text: 54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES TI0053— D 2957, JUNE 1987— REVISED JANUARY 1990 • Inputs are TTL-Voltage Compatible 54ACT11020 . . . J PACKAGE 74ACT11020 . . . D OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout
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OCR Scan
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54ACT11020,
74ACT11020
TI0053--
54ACT11020
74ACT11020
500-mA
300-mil
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PDF
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BC6MA
Abstract: thm3640f0 thm3640 Toshiba D58 THM3640F0BS/BSG-60A70
Text: TOSHIBA THM3640F0BS/BSGW70 PRELIMINARY 4,194,304 WORDS X 36 BIT DYNAMIC RAM MODULE Description The THM3640F0BS/BSG is a 4,194,304 words by 36 bits dynamic RAM module which assembled 8 pcs of TC5117400BSJ and 1 pc of TC5117440BSJ on the printed circuit board. This module is optimized for application to the systems which are
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OCR Scan
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THM3640F0BS/BSGW70
THM3640F0BS/BSG
TC5117400BSJ
TC5117440BSJ
198mW
THMxxxxxx-60)
489mW
THMxxxxxx-70)
DM16030894
M3640F0BS/BSG
BC6MA
thm3640f0
thm3640
Toshiba D58
THM3640F0BS/BSG-60A70
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PDF
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TI009
Abstract: No abstract text available
Text: 54AC11643, 74AC 11643 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS T I0095— D2957, JU LY 1987— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11643 . . . JT PACKAGE 74AC11643 . . . DW OR NT PACKAGE TOP VIEW Center-Pin V c c and GND Configurations to
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OCR Scan
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54AC11643,
I0095--
D2957,
500-mA
300-mil
54AC11643
74AC11643
TI009
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PDF
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D2957
Abstract: 1987-REVISEDAPRIL
Text: 54ACT11030,74ACT11030 8-INPUT POSITIVE-NAND GATES _ D2957. MARCH 1987-REVISEDAPRIL 1993 Inputs Are TTL*Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-PIn V^c and GNO Configurations Minimize High-Speed Switching Noise EPIC Enhanced-Perlormance Implanted
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OCR Scan
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54ACT11030
74ACT11030
D2957.
1987-REVISEDAPRIL
500-mA
300-mll
D2957,
D2957
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PDF
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74AC108
Abstract: so 54 t 74AC11066
Text: 54AC11086, 74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES TI0152— D3375, N O VEM BER 1989 • Flow-Through Architecture to Optimize PCB Layout 54AC11086 . . . J PACKAGE 74AC11086 . . . D OR N PACKAGE TOP VIEW • Center-Pin Vqc and GND Configurations to
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OCR Scan
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54AC11086,
74AC11086
TI0152--
D3375,
500-mA
300-mil
74AC108
so 54 t
74AC11066
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PDF
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v801
Abstract: tc5165165
Text: T O SH IB A THM72V8015ATG-4,-5 TENTATIVE TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT 8,388,6O8-WORD BY 72-BIT DYNAMIC RAM MODULE DESCRIPTION The THM72V8015ATG is a 8,388,608-word by 72-bit dynamic RAM module consisting of nine TC5165805AFT DRAMs on a printed circuit board. This module is optimized for applications which
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OCR Scan
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THM72V8015ATG-4
72-BIT
THM72V8015ATG
608-word
TC5165805AFT
v801
tc5165165
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PDF
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ti0041
Abstract: No abstract text available
Text: 54ACT11000, 74ACT11000 QUADRUPLE 2-INPUT POSITIVE-NAND GATES T I0041— D2957, JUNE 1967— REVISED M ARCH 1990 • Inputs are TTL-Voltage Compatible 5 4 A C T 11 0 00 . . . J P ACKA G E 7 4 A C T 1 1000 . . . D O R N PACKA GE • Flow-Through Architecture to Optimize PCB
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OCR Scan
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54ACT11000,
74ACT11000
I0041--
D2957,
500-mA
300-mil
ti0041
|
PDF
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Untitled
Abstract: No abstract text available
Text: 54AC11074,74AC11074 DUAL D-TYPE POSUIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET D2957, D E C E M B E R 1986 - REVISED A P R IL 1983 54AC11074. . . J PACKAGE 74AC11074. . . D, N, OR PW PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout
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OCR Scan
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54AC11074
74AC11074
D2957,
500-mA
300-mil
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PDF
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UC3861 application note
Abstract: No abstract text available
Text: 1 1 |application INFO available | UNITRODE UC1861-1868 UC2861-2868 UC3861-3868 Resonant-Mode Power Supply Controllers FEATURES DESCRIPTION • Controls Zero Current Switched ZCS or Zero Voltage Switched (ZVS) Quasi-Resonant Converters The UC1861-1868 family of ICs is optimized for the control of Zero Cur
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UC1861-1868
UC2861-2868
UC3861-3868
10kHz
UC3861-3868
UC3861 application note
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PDF
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