IC 7408
Abstract: IC 7812 REGULATOR IC 7812 IC TTL 7400 NEC d446c d446c data sheet IC 7408 ic 74151 IC 74153 REGULATOR IC 7912
Text: 1 of 8 Home Up Hewlett-Packard Part Number to Industry Standard HP Part Number DESCRIPTION Equivalent Part Number 1810-0076 SIP Resistor Network, 1K8 x 8 no industry number 1810-0307 RESISTOR ARRAY 316-101 100 ohms AB 1816-1104 1K ROM HP1350 Char. Gen. no industry number
|
Original
|
HP1350
82S126
1818-0373B
MK34127N
D446C-2
NEC/AMNE592
IC 7408
IC 7812
REGULATOR IC 7812
IC TTL 7400
NEC d446c
d446c
data sheet IC 7408
ic 74151
IC 74153
REGULATOR IC 7912
|
PDF
|
7054F
Abstract: BC564A HA13563 AC123A HITACHI microcontroller H8 534 manual IC 74LS47 AC538 BC245A 2SK3235 HA13557
Text: INDEX General General Information Semiconductor Packages Sales Locations Microcontroller Microcontroller General MultiChipModules Smart Card Micro. Overview Micro. Shortform Micro. Hardware Manual Micro. Program. Manual Micro. Application Notes LCD Controller / Driver
|
Original
|
2sc4537
2sc454.
2sc4591
2sc4592
2sc4593
2sc460.
2sc4628
2sc4629
2sc4643
2sc4680
7054F
BC564A
HA13563
AC123A
HITACHI microcontroller H8 534 manual
IC 74LS47
AC538
BC245A
2SK3235
HA13557
|
PDF
|
logos 4012B
Abstract: 1LB553 Rauland ETS-003 Silec Semiconductors MCP 7833 4057A transistor sr52 74c912 1TK552 74S485
Text: L p i > « , * S E m Ic O N VOLUM E 3 INTERNATIONAL INTEGRATED CIRCUITS INDEX 5th EDITION 1985 Revised June 1985 COMPILED AND PUBLISHED BY S E M IC O N IN D E X E S L IM IT E D THE SEMICON INDEX SERIES CONSISTS OF VOLUME 1 TRANSISTOR INDEX VOLUME 2 DIODE & SCR INDEX
|
OCR Scan
|
TDA1510
TDA1510A
logos 4012B
1LB553
Rauland ETS-003
Silec Semiconductors
MCP 7833
4057A
transistor sr52
74c912
1TK552
74S485
|
PDF
|
EATON CM20A
Abstract: A5 GNE mosfet Hall sensor 44e 402 2N8491 FTG 1087 S TRIAC BCR 10km FEB3T smd transistor marking 352a sharp EIA 577 sharp color tv schematic diagram MP-130 M mh-ce 10268
Text: Table of Contents N E W A R K E L E C T R O N IC S “Where serving you begins even before you call” Newark Electronics is a UNIQUE broadline distributor of electronic components, dedicated to provid ing complete service, fast delivery and in-depth inventory. Our main
|
OCR Scan
|
|
PDF
|
54LS10DMQB
Abstract: DM74LS10N 54LS10 54LS10FMQB 54LS10LMQB DM54LS10J DM54LS10W DM74LS10 DM74LS10M E20A
Text: S E M IC O N D U C T O R tm DM74LS10 Triple 3-Input NAND Gates General Description This device contains three independent gates each of which perform s the logic N AND function. Features • A lternate M ilitary/Aerospace device 54LS10 is available. C ontact a Fairchild Sem iconductor Sales
|
OCR Scan
|
DM74LS10
54LS10)
54LS10DMQB,
54LS10FMQB,
54LS10LMQB,
DM54LS10J,
DM54LS10W,
DM74LS10M
DM74LS10N
54LS10DMQB
54LS10
54LS10FMQB
54LS10LMQB
DM54LS10J
DM54LS10W
DM74LS10
E20A
|
PDF
|
54LS109
Abstract: 54LS109DMQB 54LS109FMQB DM54LS109AJ DM54LS109AW DM74LS109A DM74LS109AN J16A M16A
Text: E M IC D N D U C T O R t General Description This device contains tw o independent positive-edge-triggered J-K flip-flops w ith com plem entary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. T he triggering occurs at a vo lt
|
OCR Scan
|
DM74LS109A
16-Lead
DM74LS109AN
54LS109FMQB
DM54LS109AW
54LS109
54LS109DMQB
DM54LS109AJ
DM74LS109A
J16A
M16A
|
PDF
|
Untitled
Abstract: No abstract text available
Text: MITSUBISHI HIGH SPEED CMOS M74HC10P M74HC10DP T R IP L E 3 -IN P U T P O S IT IV E NAND GATE DESCRIPTION The M 74H C 10 is a sem iconductor integrated c ircu it con sisting of three 3-in put p o s itiv e -lo g ic NAND, PIN CONFIGURATION TOP VIEW usable as
|
OCR Scan
|
M74HC10P
M74HC10DP
|
PDF
|
74HC109P
Abstract: No abstract text available
Text: MITSUBISHI HIGH S P E E D CMOS M 74H C 109P /FP /D P DUAL i-K F L I P - F L O P WITH S E T AND R E S E T DESCRIPTION T h e M 7 4 H C 1 0 9 is a s e m ic o n d u c to r in te g r a te d c irc u it c o n PIN CONFIGURATION TOP VIEW s is tin g of tw o p o s it iv e -e d g e t r ig g e r e d J - K flip flo p s w ith in
|
OCR Scan
|
|
PDF
|
J-K Flip flops
Abstract: 74LS107 pin configuration 74LS107 74LS107* pin and application 4000B M74HC107 M74HC107P M74HC73P Toggle flip flop IC "J-K Flip flops"
Text: M IT S U B IS H I HIGH S P E E D C M O S M 74H C 107P D U A L J-K F L IP - F L O P W IT H R E S E T DESCRIPTION T h e M 7 4 H C 1 0 7 is a s e m ic o n d u c to r in te g r a te d c irc u it c o n PIN CONFIGURATION TOP VIEW s is tin g of t w o n e g a t i v e - e d g e tr ig g e r e d J - K flip flo p s w ith in
|
OCR Scan
|
M74HC107P
M74HC107
50MHz
J-K Flip flops
74LS107
pin configuration 74LS107
74LS107* pin and application
4000B
M74HC107P
M74HC73P
Toggle flip flop IC
"J-K Flip flops"
|
PDF
|
RS flip flop IC
Abstract: M74LS109AP T flip flop pin configuration Toggle flip flop IC JK flip flop IC 20-PIN toggle type flip flop ic
Text: MITSUBISHI LSTTLs M 74LS109AP DUAL J-K POSITIVE EDGE-TRIGGERED FLIP FLO P WITH S E T AND R ESE T DESCRIPTION PIN C O NFIG URATIO N TOP V IEW The M74LS109AP is a semiconductor integrated circuit containing 2 J-K positive edge-triggered flip-flop circuits
|
OCR Scan
|
M74LS109AP
M74LS109AP
16-PIN
20-PIN
RS flip flop IC
T flip flop pin configuration
Toggle flip flop IC
JK flip flop IC
toggle type flip flop ic
|
PDF
|
pin diagram of 74109
Abstract: 74109 74109 dual JK PIN CONFIGURATION 74109 TTL 74109 1N3064 1N916 74LS 74LS109 74LS109A
Text: 74109, LS109A Signetics Flip-Flops Dual J-K Positive Edge-Triggered Flip-Flop Product Specification Logic Products TYPICAL f MAX TYPICAL SUPPLY CURRENT TOTAL 74109 33MHz 9mA 74LS109A 33MHz 4mA DESCRIPTION The '109 is dual positive edge-triggered JK-type flip-flop featuring individual J, K,
|
OCR Scan
|
LS109A
1N916,
1N3064,
500ns
pin diagram of 74109
74109
74109 dual JK
PIN CONFIGURATION 74109
TTL 74109
1N3064
1N916
74LS
74LS109
74LS109A
|
PDF
|
74LS109PC
Abstract: No abstract text available
Text: 109 C O N N E C T IO N D IA G R A M PINOUT A /54S /74S 109 v o4LS/74LS109 DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP D E S C R IP T IO N — The '109 consists of tw o high speed, com pletely indepen dent transition clocked J K flip-flops. The clocking operation is independent
|
OCR Scan
|
o4LS/74LS109
54/74S
54/74LS
74LS109PC
|
PDF
|
74LS109D
Abstract: 4151 cp IR 9024 74LS109PC 74S109
Text: I 1 NATIONAL SEMICOND -CLOGIO OSE D 1 5 0 1 1 5 2 □Dt,37flS 1 | T~ ¥ 6 - 0 7 - 0 7 109 C O N N E C T IO N D IA G R A M P IN O U T A 54S/74S109 54LS/74LS109 DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP D E S C R IP T IO N — T he ’109 co n sists of two high speed, com pletely indepen
|
OCR Scan
|
37flS
54S/74S109
54LS/74LS109
54/74S
54/74LS
74LS109D
4151 cp
IR 9024
74LS109PC
74S109
|
PDF
|
LS 107
Abstract: 74LS107P
Text: I NATIONAL SEMICOND { L O G I O 05E D | b S D H E S 107 DDb370G 7^ 5 | t/1-07-07 C O N N E C T IO N D IA G R A M P IN O U T A 54/74107 54LS/74LS107 DUAL JK FLIP-FLOP With Separate Clears and Clocks D E S C R IP T I O N — T he '107 dual J K master/slave flip-flops have a separate
|
OCR Scan
|
DDb370G
54LS/74LS107
t/1-07-07
D0b37
54/74LS
CLS107)
//07-3X
LS 107
74LS107P
|
PDF
|
|
|
74LS109AP
Abstract: M74LS109 flip flop RS M74LS109AP
Text: MITSUBISHI LSTTLs M 74LS109A P DUAL J-K P O S IT IV E EDGE-TRIGGERED F L IP FLOP W IT H SET AND RESET DESCRIPTION PIN CONFIGURATION TOP VIEW The M74LS109AP is a semiconductor integrated circu it containing 2 J-K positive edge-triggered flip -flo p circuits
|
OCR Scan
|
74LS109A
M74LS109AP
b2LHfl27
0013Sbl
14-PIN
16-PIN
20-PIN
74LS109AP
M74LS109
flip flop RS
|
PDF
|
74LS10P
Abstract: M74LS10P
Text: M IT S U B IS H I L S T T L s M 74LS10P TRIPLE 3-IN P U T POSITIVE NAND GATES DESCRIPTION The M 74LS 10P is a semiconductor integrated circuit containing three triple-input positive N A N D and negative N O R gates. FEATURES • High breakdown input voltage V | ^ 15 V
|
OCR Scan
|
74LS10P
500ns,
b2LHfl27
0013Sbl
14-PIN
16-PIN
20-PIN
74LS10P
M74LS10P
|
PDF
|
74ls109
Abstract: No abstract text available
Text: MOTOROLA SN54/74LS109A DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP T h e S N 5 4 /7 4 L S 1 0 9 A c o n sists of tw o high sp e e d c o m p le te ly in d e p e n d e n t tra n s itio n clo cke d JK flip -flo p s. T h e c lo c k in g o p e ra tio n is in d e p e n d e n t o f rise
|
OCR Scan
|
SN54/74LS109A
751B-03
74ls109
|
PDF
|
Untitled
Abstract: No abstract text available
Text: GD54/74LS107 A DUAL NEGATIVE-EDGE-TRIGGERED MASTER-SLAVE J-K FLIP-FLOPS WITH CLEAR,AND COMPLEMENTARY OUTPUTS Features • Negative edge-triggering • Independent input/output terminals for each flip-flop. • Direct reset input • Q and 5 outputs Pin C o n fig u ra tio n
|
OCR Scan
|
GD54/74LS107
GD54/74LS107A
|
PDF
|
74LSOO
Abstract: 1S2074 HD74LS109A HD74LS109
Text: H D 74LS109A . Dual J-K Positive-edge-triggered Flip-Flops with Preset and Clear IP IN ARRANGEMENT •REC O M M EN D ED OPERATING CONDITIONS S ym bol Item fro c k C lock fre q u e n c y C lo c k High P u ls e w idth Sr.*.v* low “ H " D a ta S e tu p tim e
|
OCR Scan
|
HD74LS109A.
QQ14CI14
DG-14
06max
20-IU8
OG-16
DG-24
74LSOO
1S2074
HD74LS109A
HD74LS109
|
PDF
|
74LS109A
Abstract: SN54/74LS109A truth table NOT gate 74
Text: M M O T O R O L A SN54/74LS109A D E S C R IP T IO N — T h e S N 5 4 L S /7 4 L S 1 0 9 A c o n s is ts of tw o hig h speed c o m p le te ly in d e p e n d e n t tra n s itio n clo cked J K flip -flo p s . T he clo c k in g o p e ra tio n is in d e p e n d e n t o f rise and fa ll tim e s o f th e c lo c k w a v e fo rm . The
|
OCR Scan
|
SN54LS/74LS109A
SN54/74LS109A
Inp125
74LS109A
SN54/74LS109A
truth table NOT gate 74
|
PDF
|
Untitled
Abstract: No abstract text available
Text: H D 74LS109A . •REC O M M EN D ED OPERATING Symbol Item /„O 'k Clock frequency Clock High P u lse width Sr.*.v* low “H "D ata Setup tim e “ L 'D a ta th Hold tim e Note 11 The arrow indicates the rising edge. Dual J-K Positive-edge-triggered Flip-Flops with Preset and Clear)
|
OCR Scan
|
74LS109A
T-90-10
74LSOO
ib203
|
PDF
|
74LS107n
Abstract: 74107PC IC 74LS107
Text: 107 CONNECTION DIAGRAM P IN O U T A oft 54/74107 O ' 54LS/74LS107^ n o r D UAL JK FLIP-FLO P With Separate Clears and Clocks Ji ^ DESCRIPTION— T he '107 dual J K master/slave flip-flops have a separate clo ck for each flip-flop. Inputs to the master section are controlled by the
|
OCR Scan
|
54LS/74LS107^
54/74LS
CLS107)
74LS107n
74107PC
IC 74LS107
|
PDF
|
Untitled
Abstract: No abstract text available
Text: GD54/74LS109A DUAL POSITIVE-EDGE- TRIGGERED J-K FLIP-FLOPS Feature Pin Configuration • Positive Edge-Triggering • Direct Set and reset inputs • J and K inputs • Q and Q outputs Vcc CLR2 J2 K2 C LK 2 PR2 Q2 QS R RRRFI R HR y Description This device contains two independent positiveedge-triggered J-K flip-flops with complementary out
|
OCR Scan
|
GD54/74LS109A
|
PDF
|
IC 74107
Abstract: IC 74LS107 74LS107 LS107
Text: Signelics 74107, LS107 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION transferred to the slave on the H IG H -toLO W Clock transition. For these devices TYPICAL f MAX TYPICAL SUPPLY CURRENT TOTAL 74107 20MHz 20mA 74LS107 45MHz
|
OCR Scan
|
LS107
1N916,
1N3064,
500ns
500ns
IC 74107
IC 74LS107
74LS107
LS107
|
PDF
|
