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    OC3 TUBE Search Results

    OC3 TUBE Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    82V3010PVG Renesas Electronics Corporation T1/E1/OC3 Telecom Clock Generator With Dual Reference Inputs Visit Renesas Electronics Corporation
    82V3010PVG8 Renesas Electronics Corporation T1/E1/OC3 Telecom Clock Generator With Dual Reference Inputs Visit Renesas Electronics Corporation
    82V3155PVG8 Renesas Electronics Corporation Enhanced T1/E1/OC3 WAN PLL With Dual Reference Inputs Visit Renesas Electronics Corporation
    82V3012PVG Renesas Electronics Corporation T1/E1/OC3 WAN PLL With Dual Reference Inputs Visit Renesas Electronics Corporation
    82V3012PVG8 Renesas Electronics Corporation T1/E1/OC3 WAN PLL With Dual Reference Inputs Visit Renesas Electronics Corporation

    OC3 TUBE Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    Untitled

    Abstract: No abstract text available
    Text: INTEGRATED CIRCUITS DATA SHEET TZA3033 SDH/SONET STM1/OC3 transimpedance amplifier Objective specification File under Integrated Circuits, IC19 1998 Jul 08 Philips Semiconductors Objective specification SDH/SONET STM1/OC3 transimpedance amplifier TZA3033 FEATURES


    Original     		TZA3033 SA5223. TZA3033T TZA3033U pan9352 TZA3033T/C2 TZA3033T/C3 PDF

    TZA3034TD

    Abstract: TZA3034TD-T
    Text: INTEGRATED CIRCUITS DATA SHEET TZA3034 SDH/SONET STM1/OC3 postamplifier Product specification Supersedes data of 1999 Mar 16 File under Integrated Circuits, IC19 1999 Nov 03 Philips Semiconductors Product specification SDH/SONET STM1/OC3 postamplifier TZA3034


    Original     		TZA3034 NE/SA5224 NE/SA5225 TZA3034TD-T TZA3034U/C2 OT109 TZA3034TD PDF

    GR-1244-CORE

    Abstract: MT9045 MT9045AN MT9045AN1 MT9045ANR TR62411 74HC14 application oscillator 20mhz
    Text: MT9045 T1/E1/OC3 System Synchronizer Data Sheet Features • February 2005 Supports AT&T TR62411 and Bellcore GR-1244CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces Ordering Information MT9045AN 48 Pin SSOP MT9045ANR 48 Pin SSOP


    Original     		MT9045 TR62411 GR-1244CORE MT9045AN MT9045ANR MT9045AN1 MT9045ANR1 GR-1244-CORE MT9045 MT9045AN MT9045AN1 MT9045ANR 74HC14 application oscillator 20mhz PDF

    Untitled

    Abstract: No abstract text available
    Text: MK2049-36 3.3 Volt Communications Clock PLL Description Features The MK2049-36 is a Phased Locked Loop PLL based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3 and


    Original     		MK2049-36 MK2049-36 PDF

    Untitled

    Abstract: No abstract text available
    Text: MK2049-36 3.3 Volt Communications Clock PLL Description Features The MK2049-36 is a Phased Locked Loop PLL based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3 and


    Original     		MK2049-36 MK2049-36 PDF

    siemens Logo 230 rc manual

    Abstract: No abstract text available
    Text: MT9044 T1/E1/OC3 System Synchronizer Data Sheet Features • November 2004 Supports AT&T TR62411 and Bellcore GR-1244CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ITU-T G.813 Option 1 clocks for 2048 kbit/s interfaces


    Original     		MT9044 TR62411 GR-1244CORE siemens Logo 230 rc manual PDF

    MAN05

    Abstract: MK2049-34 MK2049-36 MK2049-36SI MK2049-45 TR62411 ETS300 GR-1244
    Text: DATASHEET MK2049-36 3.3 VOLT COMMUNICATIONS CLOCK PLL Description Features The MK2049-36 is a Phased Locked Loop PLL based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3 and other communications


    Original     		MK2049-36 MK2049-36 MAN05 MK2049-34 MK2049-36SI MK2049-45 TR62411 ETS300 GR-1244 PDF

    ETS300

    Abstract: GR-1244 MAN05 MK2049-34 MK2049-36 MK2049-45 TR62411
    Text: DATASHEET MK2049-36 3.3 VOLT COMMUNICATIONS CLOCK PLL Description Features The MK2049-36 is a Phased Locked Loop PLL based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3 and other communications


    Original     		MK2049-36 MK2049-36 ETS300 GR-1244 MAN05 MK2049-34 MK2049-45 TR62411 PDF

    Untitled

    Abstract: No abstract text available
    Text: MK2049-36 3.3V Communications Clock PLL Description Features The MK2049-36 is a Phased Locked Loop PLL based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3 and


    Original     		MK2049-36 MK2049-36 PDF

    Untitled

    Abstract: No abstract text available
    Text: MK2049-36 3.3V Communications Clock PLL Description Features The MK2049-36 is a Phased Locked Loop PLL based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3 and


    Original     		MK2049-36 MK2049-36 PDF

    100BASE-LX10

    Abstract: GR-468
    Text: Fast Ethernet SFP Transceiver SP-FE-LX Features • Compliant with OC3/STM-1, IEEE 802.3ah, 100BASE-LX10 • Single 3.3 V Supply • 10 dB Minimum Link Budget • 15 km Minimum Reach • 1310nm FP Laser • Commercial Temperature Available -Cxx • Industrial Temperature Available (-Txx)


    Original     		100BASE-LX10 1310nm SFF-8074i GR-468 SFF-8472 LUMNDS856-Dec0806 100BASE-LX10 PDF

    ETS300

    Abstract: GR-1244 MAN05 MK2049-34 MK2049-36 MK2049-36SI MK2049-36SITR MK2049-45 TR62411 MK2049-36SILF
    Text: DATASHEET MK2049-36 3.3 VOLT COMMUNICATIONS CLOCK PLL Description Features The MK2049-36 is a Phased Locked Loop PLL based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3 and other communications


    Original     		MK2049-36 MK2049-36 lead284 199707558G ETS300 GR-1244 MAN05 MK2049-34 MK2049-36SI MK2049-36SITR MK2049-45 TR62411 MK2049-36SILF PDF

    ETS300

    Abstract: GR-1244 MAN05 MK2049-34 MK2049-36 MK2049-45 TR62411
    Text: DATASHEET MK2049-36 3.3 VOLT COMMUNICATIONS CLOCK PLL Description Features The MK2049-36 is a Phased Locked Loop PLL based clock synthesizer that accepts multiple input frequencies. With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3 and other communications


    Original     		MK2049-36 MK2049-36 ETS300 GR-1244 MAN05 MK2049-34 MK2049-45 TR62411 PDF

    siemens Logo 230 rc manual

    Abstract: schmit GTO MODULE GR-1244-CORE MT9044 MT9044AL MT9044AL1 MT9044AP MT9044AP1 MT9044APR
    Text: MT9044 T1/E1/OC3 System Synchronizer Data Sheet Features • November 2005 Supports AT&T TR62411 and Bellcore GR-1244CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces • Supports ITU-T G.813 Option 1 clocks for 2048 kbit/s interfaces


    Original     		MT9044 TR62411 GR-1244CORE MT9044AP MT9044AL MT9044APR MT9044APR1 MT9044AP1 MT9044AL1 siemens Logo 230 rc manual schmit GTO MODULE GR-1244-CORE MT9044 MT9044AL MT9044AL1 MT9044AP MT9044AP1 MT9044APR PDF

    ICS894D115I-01

    Abstract: tube OC3 ICS894D115BGI-01 ICS894D115I-04 ICS894D115I vsc8115 OC3 Tube
    Text: ICS894D115I-01 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE General Description Features The ICS894D115I-01 is a clock and data recovery circuit. The device is designed to extract the clock HiPerClockS signal from a NRZ-coded STM-4 OC-12/STS-12 or


    Original     		ICS894D115I-01 OC-12/STM-4 ICS894D115I-01 OC-12/STS-12) tube OC3 ICS894D115BGI-01 ICS894D115I-04 ICS894D115I vsc8115 OC3 Tube PDF

    Untitled

    Abstract: No abstract text available
    Text: ICS894D115I-01 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE General Description Features The ICS894D115I-01 is a clock and data recovery circuit. The device is designed to extract the clock HiPerClockS signal from a NRZ-coded STM-4 OC-12/STS-12 or


    Original     		ICS894D115I-01 OC-12/STM-4 ICS894D115I-01 OC-12/STS-12) PDF

    ICS894D115I-04

    Abstract: led clock circuit diagram ICS894D115I-01 ICS894D115AGI-04 ICS894D115I
    Text: ICS894D115I-04 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE General Description Features The ICS894D115I-04 is a clock and data recovery circuit. The device is designed to extract the clock HiPerClockS signal from a NRZ-coded STM-4 OC-12/STS-12 or


    Original     		ICS894D115I-04 OC-12/STM-4 ICS894D115I-04 OC-12/STS-12) led clock circuit diagram ICS894D115I-01 ICS894D115AGI-04 ICS894D115I PDF

    Untitled

    Abstract: No abstract text available
    Text: ICS894D115I-04 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE General Description Features The ICS894D115I-04 is a clock and data recovery circuit. The device is designed to extract the clock HiPerClockS signal from a NRZ-coded STM-4 OC-12/STS-12 or


    Original     		ICS894D115I-04 OC-12/STM-4 ICS894D115I-04 OC-12/STS-12) PDF

    OC3 Tube

    Abstract: C813C Nippon capacitors
    Text: PRELIMINARY ICS894D115I-01 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE General Description Features The ICS894D115I-01 is a clock and data recovery circuit. The device is designed to extract the clock HiPerClockS signal from a NRZ-coded STM-4 OC-12/STS-12 or


    Original     		OC-12/STM-4 ICS894D115I-01 OC-12/STS-12) 08MHz 52MHz) 44MHz ICS894D115I EPAD441764 OC3 Tube C813C Nippon capacitors PDF

    OC3 Tube

    Abstract: tube OC3 SP-03-MX
    Text: OC-3 SFP Transceiver SP-03-MX Features • Data Rate 155.52 Mb/s • Single 3.3V Supply • 2 km Reach for 62.5/125 mm MMF 500 MHz•km • 1310nm FP Laser • SFP MSA SFF-8074i Compliant • Compliant with GR-253 OC-3 SR1 • Telcordia GR-468 Compliant


    Original     		SP-03-MX 1310nm SFF-8074i GR-253 GR-468 155MHz LUMNDS1511-May0406 OC3 Tube tube OC3 SP-03-MX PDF

    EIA-625

    Abstract: ecl 10K signetics LUCENT InGaAs 1345FMPC GR-253-CORE TR-NWT-000468 pin optical fiber lucent DS99-073LWP
    Text: Data Sheet January 2000 1345-Type Receiver with Clock Recovery and Data Retiming Applications • Telecommunications — Inter- and intraoffice SONET/ITU-T SDH — Subscriber loop — Metropolitan area networks ■ High-speed data communications Description


    Original     		1345-Type 20-pin, 20-pin GR-253-CORE) DS00-099OPTO DS99-071LWP) EIA-625 ecl 10K signetics LUCENT InGaAs 1345FMPC GR-253-CORE TR-NWT-000468 pin optical fiber lucent DS99-073LWP PDF

    lucent OC12 receiver

    Abstract: Lucent receiver GR-253-CORE TR-NWT-000468 8833 signetics 1345cnpc
    Text: Data Sheet January 1999 1345-Type Receiver with Clock Recovery and Data Retiming Applications • Telecommunications — Inter- and intraoffice SONET/ITU-T SDH — Subscriber loop — Metropolitan area networks ■ High-speed data communications Description


    Original     		1345-Type 20-pin, 20-pin GR-253-CORE) DS99-071LWP DS98-358LWP) lucent OC12 receiver Lucent receiver GR-253-CORE TR-NWT-000468 8833 signetics 1345cnpc PDF

    OC3 Tube

    Abstract: od3 tube od3 Voltage Regulator ob3 tube tube OC3 0C3 TUBE gas filled voltage regulator ST-12 90 VOLTS REGULATOR Scans-0017246
    Text: a:\ m y S Y L V A N IA 0B3 engineering data service 0C3, 0D3 MECHANICAL DATA B u l b . ST-12 B a s e . B6-3, Small Shell Octal, 6-Pin


    OCR Scan     		ST-12 OC3 Tube od3 tube od3 Voltage Regulator ob3 tube tube OC3 0C3 TUBE gas filled voltage regulator ST-12 90 VOLTS REGULATOR Scans-0017246 PDF

    lucent OC12 receiver

    Abstract: No abstract text available
    Text: Data Sheet September 1998 group y' Lucent Technologies Bell Labs Innovations 1345-Type Receiver with Clock Recovery and Data Retiming Applications • Telecommunications — Inter- and intraoffice SONET/ITU-T SDH — Subscriber loop — Metropolitan area networks


    OCR Scan     		1345-Type OC-12 GR-253-CORE DS98-358LWP lucent OC12 receiver PDF