NS-25/E2 TO Search Results

NS-25/b2

Abstract: ns-25 HL-Planartechnik INCLINOMETER sensor for inclinometer Electronic PC board inclinometer sensor NS-25/E2 To preset Potentiometers ns25
Contextual Info: Inclination Sensor ±25° NS25/E2 APPLICATION NOTES General Information The NS-25/E2 inclinometer is designed for OEM applications. It is a newly developed sensor, manufactured in modern micro system technology. Basically, the sensor consists of a measuring ceIl, manufactured in thin-film technique which is mounted

MCM6264C

Abstract: 6264C cga motorola mcm6264p
Contextual Info: MOTOROLA SC MEMORY/ASIC MbE ]> b3b7251 Q Q à ü a in T 1 3 MOT3 da1 sheet Order this data by MCM6264C/D j-_ MOTOROLA m S E M IC O N D U C T O R TECHNICAL DATA M C M 6264C 8K x 8 Bit Fast Static RAM Industrial Temperature Range: -4 0 to 85°C The MCM6264C is a 64,536 bit static random access memory organized as

E2 SMD Transistor

Abstract: CY62148 E0 SMD CODE 2M x 16 SRAM
Contextual Info: CYM8210BPM 2M x 16 Static RAM Module Features structed using eight 512K x 8 SRAMs CY62148 in SOJ packages mounted on an epoxy laminate board with pins. • High-density 32-megabit SRAM module • Low active power Writing to each byte is accomplished by enabling the appropriate Chip Select (E0, E1, E2, E3) and write enable (WH or WL).

Contextual Info: ELECTRONIC DESIGNS INC fiS D e | 353011M 00D0141 7 I 1 -4 6 * 3 -1 2 EDH 8808ACL 15/20 Monolithic The future. . . today. 8Kx8 Static RAM CMOS, Monolithic Features The EDH 8808ACL is a high performance, low power, CMOS Static RAM utilizing 6 transistor cell

67164

Abstract: 0E12 UT67164 SRAM flatpack
Contextual Info: Standard Products UT67164 Radiation-Hardened 8K x 8 SRAM - SEU Hard Data Sheet December 1999 FEATURES q 55ns maximum address access time, single-event upset less than 1.0E-10 errors//bit day -55oC to 125+oC q Asynchronous operation for compatibility with industrystandard 8K x 8 SRAM

Contextual Info: B EH EDH8808ACL 8 5 /1 0 /1 2 /1 5 /2 0 Monolithic The fu tu re . . . today. 8Kx8 Static RAM CMOS, Low Power Monolithic Features 64K bit CMOS Static RAM Organized as 8,192 x8 Bits • Access Times of 85,100, j l 20,150 and 200ns • E and G Functions for Bus Control

Contextual Info: M69AW024B 16 Mbit 1M x16 3V Asynchronous 1T/1C SRAM PRELIMINARY DATA FEATURES SUMMARY • SUPPLY VOLTAGE: 2.7 to 3.3V ■ ACCESS TIME: 60ns, 70ns ■ LOW STANDBY CURRENT: 70µA ■ DEEP POWER DOWN CURRENT: 10µA ■ LOW VCC DATA RETENTION: 2.3V COMPATIBLE WITH STANDARD LPSRAM

8x10m

Contextual Info: M68AW512D 8 Mbit 512K x16 3.0V Asynchronous SRAM FEATURES SUMMARY • SUPPLY VOLTAGE: 2.7 to 3.6V ■ 512K x 16 bits SRAM with OUTPUT ENABLE ■ EQUAL CYCLE and ACCESS TIMES: 55ns ■ LOW STANDBY CURRENT ■ ■ LOW VCC DATA RETENTION: 1.5V TRI-STATE COMMON I/O

Contextual Info: M68AW512DL 8 Mbit 512K x16 3.0V Asynchronous SRAM FEATURES SUMMARY • SUPPLY VOLTAGE: 2.7 to 3.6V ■ 512K x 16 bits SRAM with OUTPUT ENABLE ■ EQUAL CYCLE and ACCESS TIMES: 55ns ■ LOW STANDBY CURRENT ■ ■ LOW VCC DATA RETENTION: 1.5V TRI-STATE COMMON I/O

M69AW024BE

Abstract: TFBGA48
Contextual Info: M69AW024BE 16 Mbit 1M x16 3V Asynchronous PSRAM FEATURES SUMMARY • ■ ■ ■ ■ ■ SUPPLY VOLTAGE: 2.7 to 3.3V ACCESS TIME: 60ns LOW STANDBY CURRENT: 70µA DEEP POWER DOWN CURRENT: 10µA COMPATIBLE WITH STANDARD LPSRAM TFBGA48 PACKAGE RoHS COMPLIANT

tpd1221

Contextual Info: M68AW512D 8 Mbit 512K x16 3.0V Asynchronous SRAM FEATURES SUMMARY • SUPPLY VOLTAGE: 2.7 to 3.6V ■ 512K x 16 bits SRAM with OUTPUT ENABLE ■ EQUAL CYCLE and ACCESS TIMES: 55, 70ns ■ LOW STANDBY CURRENT ■ LOW VCC DATA RETENTION: 1.5V ■ TRI-STATE COMMON I/O

TFBGA48

Abstract: M68AW512D
Contextual Info: M68AW512D 8 Mbit 512K x16 3.0V Asynchronous SRAM FEATURES SUMMARY • ■ ■ ■ ■ ■ ■ SUPPLY VOLTAGE: 2.7 to 3.6V 512K x 16 bits SRAM with OUTPUT ENABLE EQUAL CYCLE and ACCESS TIMES: 55, 70ns LOW STANDBY CURRENT LOW VCC DATA RETENTION: 1.5V TRI-STATE COMMON I/O

20E1

Abstract: A310 G000137
Contextual Info: 3230114 E LE C TR O N IC D E S IG N S 85D IN C ELE CT RON IC DESIGNS INC AS r 00129 DEj B S 3 D i m T -4 6 -2 3 -1 2 0Q0D15T t, | ~ EDH 8808AC 70/10/12/15 LP Monolithic The fu tu re . .today. 8KxS Static RAM CMOS, Low Power Monolithic Features The EDH 8808AC-LP is a high performance, low

MCM6264DC-55

Contextual Info: MOTOROLA SC MEMORY/ASIC 4 bE D b 3 b 7 2 Sl OQflOfi?! 2 ^ M 0T3 > 4 i r 2 a - 12- order this data sheet by MCM6264D-C/D MOTOROLA SEMICONDUCTOR TECHNICAL DATA M CM 6 2 6 4 0 -0 8K x 8 Bit Fast Static RAM Industrial Temperature Range: -40 to 85°C The MCM6264D-C is a 64,536 bit static random access memory organized as

TMS62828L-12

Contextual Info: TMS62828L 1,048,576-BIT LOW-POWER STATIC RANDOM-ACCESS MEMORY JANUARY 1990 * Organization . . . 131,072 x 8 DK AND NW PACKAGES TOP VIEW * Single 5-V Power Supply (10% Tolerance) NC 0 1 L A16 C 2 A14 0 3 A12 0 4 A7 c 5 * High-Density Packaging: — Plastic 32-pin 600-Mil Duai-ln-Line

tefr1

Abstract: 0E12 UT67164
Contextual Info: Standard Products UT67164 Radiation-Hardened 8K x 8 SRAM - SEU Hard Data Sheet December 1997 FEATURES q 55ns maximum address access time, single-event upset less than 1.0E-10 errors//bit day -55oC to 125+oC q Asynchronous operation for compatibility with industrystandard 8K x 8 SRAM

M68AW512D

Abstract: TFBGA48
Contextual Info: M68AW512D 8 Mbit 512K x16 3.0V Asynchronous SRAM FEATURES SUMMARY • SUPPLY VOLTAGE: 2.7 to 3.6V ■ 512K x 16 bits SRAM with OUTPUT ENABLE ■ EQUAL CYCLE and ACCESS TIMES: 55, 70ns ■ LOW STANDBY CURRENT ■ LOW VCC DATA RETENTION: 1.5V ■ TRI-STATE COMMON I/O

SO32

Abstract: M68AF127BL PDIP32
Contextual Info: M68AF127BL 1Mbit 128K x8 , 5V Asynchronous SRAM FEATURES SUMMARY • SUPPLY VOLTAGE: 4.5 to 5.5V ■ 128K x 8 bits SRAM with OUTPUT ENABLE ■ EQUAL CYCLE and ACCESS TIMES: 55ns ■ LOW STANDBY CURRENT ■ ■ LOW VCC DATA RETENTION: 2V TRI-STATE COMMON I/O

32-PIN

Abstract: SOJ32-P-300
Contextual Info: LH521007C CMOS 128K x 8 Static RAM Data Sheet When both Chip Enables are active and W is inactive, a static Read will occur at the memory location specified by the address lines. G must be brought LOW to enable the outputs. Since the device is fully static in operation,

SOJ32

Abstract: 32-PIN SOJ32-P-300 LH521007ck
Contextual Info: LH521007C CMOS 128K x 8 Static RAM Data Sheet When both Chip Enables are active and W is inactive, a static Read will occur at the memory location specified by the address lines. G must be brought LOW to enable the outputs. Since the device is fully static in operation,

0E12

Abstract: UT67164
Contextual Info: Standard Products UT67164 Radiation-Hardened 8K x 8 SRAM - SEU Hard Data Sheet January 2002 FEATURES q 55ns maximum address access time, single-event upset less than 1.0E-10 errors//bit day -55o C to 125+oC q Asynchronous operation for compatibility with industrystandard 8K x 8 SRAM

Contextual Info: M68AR512D 8 Mbit 512Kb x16 1.8V Asynchronous SRAM FEATURES SUMMARY • SUPPLY VOLTAGE: 1.65V to 1.95V ■ 512Kb x16 bit SRAM with OUTPUT ENABLE ■ EQUAL CYCLE and ACCESS TIMES: 55ns, 70ns ■ SINGLE BYTE READ/WRITE ■ LOW STANDBY CURRENT ■ LOW VCC DATA RETENTION: 1.0V

Contextual Info: M69AW024B 16 Mbit 1M x16 3V Asynchronous PSRAM PRELIMINARY DATA FEATURES SUMMARY • ■ ■ ■ ■ ■ SUPPLY VOLTAGE: 2.7 to 3.3V ACCESS TIME: 60ns, 70ns LOW STANDBY CURRENT: 70µA DEEP POWER DOWN CURRENT: 10µA LOW VCC DATA RETENTION: 2.3V COMPATIBLE WITH STANDARD LPSRAM

M69AW024B

Abstract: TFBGA48
Contextual Info: M69AW024B 16 Mbit 1M x16 3V Asynchronous PSRAM FEATURES SUMMARY • ■ ■ ■ ■ ■ SUPPLY VOLTAGE: 2.7 to 3.3V ACCESS TIME: 60ns, 70ns LOW STANDBY CURRENT: 70µA DEEP POWER DOWN CURRENT: 10µA LOW VCC DATA RETENTION: 2.3V COMPATIBLE WITH STANDARD LPSRAM