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    NRZI DECODER Search Results

    NRZI DECODER Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TC4511BP Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, BCD-to-7-Segment Decoder, DIP16 Visit Toshiba Electronic Devices & Storage Corporation
    74HC4051FT Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, SP8T(1:8)/Analog Multiplexer, TSSOP16B, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    74HC4051D Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, SP8T(1:8)/Analog Multiplexer, SOIC16, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    HC1-55564-9 Rochester Electronics LLC HC1-55564 - CVSD Codec, CVSD Visit Rochester Electronics LLC Buy
    MM54C42J/B Rochester Electronics LLC 54C42 - Decoder/Driver Visit Rochester Electronics LLC Buy

    NRZI DECODER Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    nmea 0183 buffer

    Abstract: nrzi Decoder nrzi GMSK nmea buffer GMSK AIS nmea NMEA-0183 nrzi HDLC GMSK applications
    Text: RXDATA UART Detector Buffer TXDATA Receive Functions BURSTDET NMEA 0183 Arbiter and Formatter RX1FB RX1N GMSK Decoder NRZI Decoder HDLC Decoder Buffer GMSK Decoder NRZI Decoder HDLC Decoder Buffer Rx1 GMSK AIS Input 1 VBIAS Mux RX2FB RX2N VBIAS Rx2 GMSK AIS


    Original     		7032/7042FI-2 nmea 0183 buffer nrzi Decoder nrzi GMSK nmea buffer GMSK AIS nmea NMEA-0183 nrzi HDLC GMSK applications PDF

    Untitled

    Abstract: No abstract text available
    Text: SL2002 * DUAL CHANNEL NRZI ENCODER / DECODER ^PRELIMINARY PIN CONFIGURATION FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ Two independent Digital Phase Lock Loop circuits Two independent Full Duplex channels NRZI Encoder/Decoder DPLL runs off 16x clock Crystal o rT T L clock inputs for DPLL


    OCR Scan     		SL2002 16xCLK-OUT 4160-B PDF

    CY7C42X5

    Abstract: CY7C9689A CY7C9689A-AC
    Text: CY7C9689A TAXI -compatible HOTLink Transceiver Features • Second-generation HOTLink technology ■ AMD™ AM7968/7969 TAXIchip™-compatible ■ 8-bit 4B/5B or 10-bit 5B/6B NRZI encoded data transport ■ 10-bit or 12-bit NRZI pre-encoded bypass data transport


    Original     		CY7C9689A AM7968/7969 10-bit 12-bit 256-character 200-MBaud CY7C42X5 CY7C9689A CY7C9689A-AC PDF

    4b/5b encoder

    Abstract: CY7C42X5 CY7C9689 CY7C9689-AC
    Text: V CYPRESS PRELIMINARY CY7C9689 TAXI Compatible HOTLink™ Transceiver Features Second-generation HOTLink™ technology AMD™ AM7968/7969 TAXIchip™ compatible 8-bit 4B/5B or 10-bit 5B/6B NRZI encoded data transport 10-bit or 12-bit NRZI pre-encoded bypass data


    OCR Scan     		CY7C9689 AM7968/7969 10-bit 12-bit 50-to-200 100-pin CY7C9689 4b/5b encoder CY7C42X5 CY7C9689-AC PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C9689A TAXI -compatible HOTLink Transceiver Features • Second-generation HOTLink® technology ■ AMD™ AM7968/7969 TAXIchip™-compatible ■ 8-bit 4B/5B or 10-bit 5B/6B NRZI encoded data transport ■ 10-bit or 12-bit NRZI pre-encoded bypass data transport


    Original     		CY7C9689A AM7968/7969 10-bit 12-bit 256-character 200-MBaud PDF

    Untitled

    Abstract: No abstract text available
    Text: V CYPRESS TAXI Compatible HOTLink™ Transceiver PRELIMINARY Features Second-generation HOTLink™ technology AMD™ AM7968/7969 TAXIchip™ compatible 8-bit 4B/5B or 10-bit 5B/6B NRZI encoded data transport 10-bit or 12-bit NRZI pre-encoded bypass data


    OCR Scan     		AM7968/7969 10-bit 12-bit 50-to-200 100-pin CY7C9689 PDF

    Untitled

    Abstract: No abstract text available
    Text: ^ CYPRESS PREUM INAm CY7C9689 TAXI Compatible HOTLink™ Transceiver Features Second-generation HOTLink™ technology AMD™ AM7968/7969 TAXIchip™ compatible 8-bit 4B/5B or 10-bit 5B/6B NRZI encoded data transport 10-bit or 12-bit NRZI pre-encoded bypass data


    OCR Scan     		CY7C9689 10-bit 10-bit 12-bit CY7C9689 PDF

    nrzi to nrz circuit diagram

    Abstract: SL2002 Logicstar
    Text: SL2002*. DUAL CHANNEL NRZI ENCODER / DECODER J Ü É 3L1M IN A R Y FEATURES PIN CONFIGURATION • Two in d e p e n d e n t D ig ita l Phase Lock Loop c irc u its ■ Two in d ep e nd e nt Full D uplex channels ■ NRZI E n c o d e r/D e co d e r ■ D PLL runs o ff 16x clo ck


    OCR Scan     		SL2002* 16xCLK-OUT 16x-CLK 4160-B nrzi to nrz circuit diagram SL2002 Logicstar PDF

    MUSBFSFC

    Abstract: vhdl code for 4 channel dma controller verilog code for amba ahb bus crc verilog code 16 bit AMBA BUS vhdl code vhdl code dma controller verilog code AMBA AHB verilog code for dma controller verilog code 3 bit CRC ahb bridge
    Text: Inventra MUSBFSFC USB 1.1 Full-Speed Function Controller DMA Requests Endpoint Control EP0 Control EP1 - 15 Control IN IN CPU Interface OUTIN Interrupt Control Interrupts EP Reg. Decoder Combine Endpoints RAM Controller DPLL USB NRZI Bit Stuff CRC Packet


    Original     		1300/channel) PD-40104 003a-FO MUSBFSFC vhdl code for 4 channel dma controller verilog code for amba ahb bus crc verilog code 16 bit AMBA BUS vhdl code vhdl code dma controller verilog code AMBA AHB verilog code for dma controller verilog code 3 bit CRC ahb bridge PDF

    88E3080

    Abstract: marvell ethernet marvell IEEE optical equalizer marvell ethernet switch 100BASE-FX 88E1000 marvell "READ CHANNEL" FIR ADAPTIVE EQUALIZER
    Text: 88E3080 Fast Ethernet Transceiver 88E3080 125 MHz DPLL Receiver MARVELL STRENGTHENS RX[n]+ RX[n]- AGC Gain Control FAST ETHERNET lorem ipsum INFRASTRUCTURES Fast Ethernet Transceiver S/H ADC FEFD FIR Filter Line Quality Monitor Baseline Wander Canceller NRZI


    Original     		88E3080 10Mb/ 88E3080 marvell ethernet marvell IEEE optical equalizer marvell ethernet switch 100BASE-FX 88E1000 marvell "READ CHANNEL" FIR ADAPTIVE EQUALIZER PDF

    Untitled

    Abstract: No abstract text available
    Text: PMEUMOffM^Y MX98702 100BASE-TX PMD TRANSCEIVER FEATURE * Compatible with ANSI X3T9.5 TP-PMD draft standard * Compatible with ANSI IEEE 802.3 100 Base-T fast ethernet draft standard * Integrated trans mitter and receiver with adaptive equalizer * Programmable NRZI and MLT3 selection


    OCR Scan     		MX98702 100BASE-TX 28-pin MX98702 PDF

    nrz to nrzi decoder

    Abstract: 80C152 IN SDLC PROTOCOL IN SDLC PROTOCOL core Transmit Custom Diode
    Text: Based on Intel’s 80C152 Global Serial Channel Flexible addressing schemes SDLC Single and double byte address recognition Controller Core Address filtering allowing multicast and broadcast addresses 16-bit CCITT or 32-bit frame check sequence NRZ or NRZI data encoding


    Original     		80C152 16-bit 32-bit 8XC152 nrz to nrzi decoder IN SDLC PROTOCOL IN SDLC PROTOCOL core Transmit Custom Diode PDF

    100BASE-X

    Abstract: 4B5B encoder Mlt-3 DS206 NRZI MLT-3 PMD line code MLT CS8950 4b/5b encoder 802.3 fx 100BASE-FX
    Text: CONFIDENTIAL Sampling in 1997 CS8952 #RYSTAL ,!. 100BASE-X and 10BASE-T Transceiver Features Description • Single-Chip IEEE 802.3 Physical Interface IC for 100BASE-X and 10BASE-T • Media Supported - 100BASE-TX - 10BASE-T - 100BASE-FX NRZI for fiber links


    Original     		CS8952 100BASE-X 10BASE-T 10BASE-T 100BASE-TX 100BASE-FX 4B5B encoder Mlt-3 DS206 NRZI MLT-3 PMD line code MLT CS8950 4b/5b encoder 802.3 fx PDF

    Untitled

    Abstract: No abstract text available
    Text: in te i 82588 HIGH INTEGRATION LOCAL AREA NETWORK CONTROLLER Integrates ISO Layers 1 and 2 — CSMA/CD Medium Access Control MAC — On-Chip Manchester, NRZI Encoding/Decoding — On-Chip Logic Based Collision Detect and Carrier Sense 2 Clocks per Data Transfer


    OCR Scan     		PDF

    MX98702

    Abstract: Mlt-3 mlt 22
    Text: INDEX MX98702 100BASE-TX PMD TRANSCEIVER FEATURE * Compatible with ANSI X3T9.5 TP-PMD draft standard * Compatible with ANSI IEEE 802.3 100 Base-T fast ethernet draft standard * Integrated trans mitter and receiver with adaptive equalizer * Programmable NRZI and MLT3 selection


    Original     		MX98702 100BASE-TX 28-pin MX98702 rece886-3-578-8887 CA95131 Mlt-3 mlt 22 PDF

    nrzi circuit diagram MLT-3

    Abstract: NRZI MLT-3 TP-PMD MLT 22 705
    Text: * PRELIMINARY SY87671 TP-PMD TRANSCEIVER SYNERGY SEMICONDUCTOR DESCRIPTION • Transmitter converts NRZI ECL signals to MLT-3 current driven outputs ■ Transmitter can be extremely turned pff for true quiet time ■ Receiver includes adaptive equalizer and MLT-3 to


    OCR Scan     		SY87671 32-pin 100BASE-TX) SY87671 SY87671CQ SY87671CH nrzi circuit diagram MLT-3 NRZI MLT-3 TP-PMD MLT 22 705 PDF

    ALI-25T

    Abstract: SALI-25C TXC-07225-BCPL 82528 samsung LRA
    Text: SALI-25C Device Six ATM Line Interface at 25 Mbit/s TXC-07625 DATA SHEET FEATURES DESCRIPTION • Transmission Convergence - meets ATM Forum specifications - maps ATM cells to six 25.6 Mbit/s payloads - NRZI/NRZ and 5B/4B conversions - scrambling, cell delineation and rate adaptation


    Original     		SALI-25C TXC-07625 TXC-07625-MB ALI-25T TXC-07225-BCPL 82528 samsung LRA PDF

    Untitled

    Abstract: No abstract text available
    Text: SALI-25C Device Six ATM Line Interface at 25 Mbit/s TXC-07625 DATA SHEET PRODUCT PREVIEW -•■= • Transmission Convergence - meets ATM Forum specifications - maps ATM cells to six 25.6 Mbit/s payloads - NRZ/NRZI and 5B/4B conversions - scambling, cell delineation and rate adaptation


    OCR Scan     		SALI-25C TXC-07625 sideLI-25C TXC-07625 208-Pin -58loomss TXC-07625-MB SALI-25C PDF

    IN SDLC PROTOCOL

    Abstract: 80C152
    Text: Based on Intel’s 80C152 Global Serial Channel SDLC Controller Core Flexible addressing schemes  Single and double byte address recognition  Address filtering allowing multicast and broadcast addresses 16-bit CCITT or 32-bit frame check sequence NRZ or NRZI data encoding


    Original     		80C152 16-bit 32-bit 8XC152 IN SDLC PROTOCOL PDF

    cwi 1011

    Abstract: CNC5 C3210 CTSR "BIP 109" BIP-109 CBD3 LSC 132 C1995 DP83231
    Text: DP83251 55 PLAYER TM Device FDDI Physical Layer Controller General Description Features The DP83251 DP83255 PLAYER device implements one Physical Layer (PHY) entity as defined by the Fiber Distributed Data Interface (FDDI) ANSI X3T9 5 Standard The PLAYER device contains NRZ NRZI and 4B 5B encoders and


    Original     		DP83251 DP83255 DP83m cwi 1011 CNC5 C3210 CTSR "BIP 109" BIP-109 CBD3 LSC 132 C1995 DP83231 PDF

    82588

    Abstract: ti5a manchester differential T28-F 2T24 8T24 CRC-16 CRC-32 7t53 intel 8282
    Text: 82588 HIGH INTEGRATION LOCAL AREA NETWORK CONTROLLER in te i Integrates ISO Layers 1 and 2 — CSMA/CD Medium Access Control MAC — On-Chip Manchester, NRZI Encoding/Decoding — On-Chip Logic Based Collision Detect and Carrier Sense • 2 Clocks per Data Transfer


    OCR Scan     		K-T63 82588 ti5a manchester differential T28-F 2T24 8T24 CRC-16 CRC-32 7t53 intel 8282 PDF

    Untitled

    Abstract: No abstract text available
    Text: GS9090 GenLINX III 270Mb/s Deserializer for SDI and DVB-ASI GS9090 Data Sheet Key Features Description • SMPTE 259M-C compliant descrambling and NRZI to NRZ decoding with bypass • DVB-ASI sync word detection and 8b/10b decoding • Integrated line-based FIFO for data


    Original     		GS9090 270Mb/s 259M-C 8b/10b 270Mb/s PDF

    gennum GS9091 device

    Abstract: GS9091B GS9091 cs2 105-01 305M 352M GS9090B RP168 STG719
    Text: GS9091B GENLINX III 270Mb/s Deserializer for SDI and DVB-ASI with Integrated Cable Equalizer GS9091B Data Sheet Key Features Description • SMPTE 259M-C compliant descrambling and NRZI to NRZ decoding with bypass • DVB-ASI sync word detection and 8b/10b decoding


    Original     		GS9091B 270Mb/s 259M-C 8b/10b 270Mb/s gennum GS9091 device GS9091 cs2 105-01 305M 352M GS9090B RP168 STG719 PDF

    manchester differential

    Abstract: T75A cd controller
    Text: intei 82588 HIGH INTEGRATION LOCAL AREA NETWORK CONTROLLER Integrates ISO Layers 1 and 2 — CSMA/CD Medium Access Control MAC — On-Chip Manchester, NRZI Encoding/Decoding — On-Chip Logic Based Collision Detect and Carrier Sense • 2 Clocks per Data Transfer


    OCR Scan     		PDF