MULTIBUS II Search Results

multibus

Abstract: A3P060 DPRAM mbus verilog code 16 bit processor
Contextual Info: Overview iW-Multibus II Interface controller core is used to interface the external interface signals of the processor with the Multibus interface. The Multibus can be configured as the Master/Slave mode using the DIP switches connected to the FPGA. Features

i8289

Abstract: 8289 bus controller intel d 8289 8289 bus arbiter intel 8289 8289A "INTEL" "24-PIN" CERAMIC DIP 8289
Contextual Info: P L X TECHNOLOGY CORP 32E D • bflSSlMI DQ00102 1 B P L X T*52-?3-55’ Multibus 1 & II_ Both Multibus I and Multibus II are supported by PLX ICs. PLX offers a solu­ tion which emulates the Intel 8289 but with lower power consumption 250mW and a maximum processor clock rate of 16MHz. Multibus II Inter­

intel 8289

Abstract: 8289a 8289 bus controller SJ-33 8289 bus arbiter multibus 8289 sj33 "INTEL" "24-PIN" CERAMIC DIP arbiter chips
Contextual Info: P L X TECHNOLOGY CORP 32E D • bflSSlMI DQ00102 1 B P L X T*52-?3-55’ Multibus 1 & II_ Both Multibus I and Multibus II are supported by PLX ICs. PLX offers a solu­ tion which emulates the Intel 8289 but with lower power consumption 250mW and a maximum processor clock rate of 16MHz. Multibus II Inter­

Multibus ii protocol

Abstract: Multibus arbitration protocol 486 system bus
Contextual Info: TO SHIBA INTEGRATED CIRCUIT BAC TECHNICAL D A T A BAC Bus Arbiter/Controller GENERAL DESCRIPTION ' The MULTIBUS II Bus Arbiter/Contro1ler (BAC) is an 84-pin, CMOS component that embodies the Arbitration and system control line functions of the MULTIBUS II

Multibus ii protocol

Abstract: Multibus arbitration protocol
Contextual Info: TOSHIBA INTEGRATED CIRCUIT BAC 8 4 1 1 0 TE C H N IC A L D A T A BAC Bus Arbiter/Controller GENERAL DESCRIPTION The MULTIBUS II Bus Arbiter/Controller (BAC) is an 84-pin, CMOS component that embodies the Arbitration and system control line functions of the MULTIBUS II

multibus cable

Abstract: WD1100 WD2797 WD1802 SA450 WD1010 WD1100-10 WD1100-13 Winchester connector 48 pin floppy disk motor head step
Contextual Info: W E S T E R N D IG ITAL C O R P O R A T I O N WD1002-MTB Multibus Winchester/Floppy Disk Controller • CONTROLS UP TO FOUR 5.25" FLOPPY DISK DRIVES • MULTIBUS INTERFACE • 16 BIT DATA BUS AND 24 BIT ADDRESSING • DMA CONTROL • PROGRAMMABLE DISK PARAMETERS

BAD02

Abstract: multibus II architecture specification
Contextual Info: - INTEGRATED CIRCUIT TOSHIBA MIC 84120 TECHNICAL DATA MIC MESSAGE INTERRUPT CONTROLLER GENERAL DESCRIPTION The Message Interrupt Controller (MIC) component implements a MULTIBUS II architecture unsolicited message passing protocol interrupt capability for iPSB bus agents.

Contextual Info: Stacking Connector 130 Position Mix • No solder joints, compression stacking connector • Standardized interface for Intel “MIX” Bus Module module to module and module to baseboard connector • Connector heights tailored for Multibus II environment

Contextual Info: Stacking Connector 130 Position Mix No solder joints, compression stacking surface mount connector Standardized interface for Intel “ MIX” Bus Module module to module and module to baseboard connector Connector heights tailored for Multibus II environment

Contextual Info: Stacking Connector 130 Position Mix • No solder joints, compression stacking connector • Standardized interface for Intel “ MIX” Bus Module module to module and module to baseboard connector • Connector heights tailored for Multibus II environment

82389

Abstract: Multibus arbitration protocol Multibus ii protocol multibus 290145 28100* intel intel 82389
Contextual Info: intei MULTIBUS II BUS INTERFACE SILICON PRODUCTS • • • Processor Independent Interface to the Parallel System Bus Supports co-existence of dual port and message passing communication protocols Dual Buffer Input and Output DMA capabilities MFC 82389 INTERFACES

Contextual Info: iJ ifriffli WBrj1 - - - - — -•—- DHiConnectors Global standard-bearers DIN Connectors Global advances in the manufacturing of data processing and communications equipment have maintained a new level of design standardization and compatibility such as VME and Multibus II

BA021

Contextual Info: M82389 MESSAGE PASSING COPROCESSOR A MULTIBUS II BUS INTERFACE CONTROLLER Military u Highly Integrated VLSI Device • High Performance Coprocessing Functions — Offloads CPU for Communication and Bus Interfacing — 40 Megabytes/Sec Burst Transfer Speed

BA021

Abstract: MPC32389 IEEE-1296 82389 ba021p 290145 BAD22 176526
Contextual Info: in tj 82389 MESSAGE PASSING COPROCESSOR A MULTIBUS II BUS INTERFACE CONTROLLER • Highly Integrated VLSI Device — Single-Chip Interface for the Parallel System Bus IEEE 1296 — Interrupt Handling/Bus Arbitration Functions — Dual-Buffer Input and Output DMA

82C389

Contextual Info: V LSI Technology, in c VM82C389 MESSAGE-PASSING COPROCESSOR MULTIBUS II FEATURES DESCRIPTION • Full-function, single-chip interface to Parallel System Bus PSB The VM82C389 Message-Passing Coprocessor (MPC) provides a highintegration interface solution for the

Contextual Info: 82389 MESSAGE PASSING COPROCESSOR A MULTIBUS II BUS INTERFACE CONTROLLER • Highly Integrated VLSI Device — Single-Chip Interface for the Parallel System Bus IEEE 1296 — Interrupt Handling/Bus Arbitration Functions — Dual-Buffer Input and Output DMA

solna d30

Abstract: 74AS1804 AD23-AD16 bsc5 Multibus arbitration protocol AD31-AD24 vlsi technology Multibus ii protocol 8253 programme able interface 893000
Contextual Info: f 1 V L S I Tech n o lo gy , in c . _ VM82C389 MESSAGE-PASSING COPROCESSOR MULTIBUS II FEATURES DESCRIPTION • Full-function, single-chip interface to Parallel System Bus PSB The VM82C389 Message-Passing Coprocessor (MPC) provides a high­

Contextual Info: DIN Connectors Global advances in the manufacturing of data processing and communications equipment have established a new level of design standardization and compatibility such as VME and Multibus II structures. Standardized connectors and compo­ nents, like DIN 41612 connectors, allow manufac­

82389

Abstract: Multibus ii protocol BUS22 B1 intel 82389 Multibus II Bus Interface Controller IEEE-1296 Multibus arbitration protocol multibus II architecture specification multibus multibus ARCHITECTURE
Contextual Info: 82389 Message Passing Coprocessor A Multibus II Bus Interface Controller Datasheet Product Features • ■ Highly Integrated VLSI Device — Single-Chip Interface for the Parallel System Bus IEEE 1296 — Interrupt Handling/Bus Arbitration Functions — Dual-Buffer Input and Output DMA

Contextual Info: In te l 82389 MESSAGE PASSING COPROCESSOR A MULTIBUS II BUS INTERFACE CONTROLLER • Highly Integrated VLSI Device -Single-Chip Interface for the Parallel System Bus IEEE 1296 — Interrupt Handling/Bus Arbitration Functions — Dual-Buffer Input and Output DMA

Multibus arbitration protocol

Abstract: multibus II architecture specification BA026
Contextual Info: 82389 MESSAGE PASSING COPROCESSOR A MULTIBUS II BUS INTERFACE CONTROLLER • Highly Integrated VLSI Device — Single-Chip Interface for the Parallel System Bus IEEE 1296 — Interrupt Handling/Bus Arbitration Functions — Dual-Buffer Input and Output DMA

multibus

Contextual Info: Laborkarte RE333-LF - Epoxyd FR4 1,5 mm, zweiseitig 35 µm CU durchkontaktiert - heißverzinnt (HAL-leadfree) - System Multibus II - 79 x 80 Lötinseln 2,0 mm Ø - Lochraster 2,54 x 2,54 mm - Lochdurchmesser 1,0 mm - Steckverbinder 32/ 64/ 96-polig DIN 41612 Bauform C

28100* intel

Contextual Info: intel. MIX I/O MODULES 281009-42 MIX 450 ASYNCHRONOUS TERMINAL CONTROLLER The MIX 450 term inal module, when combined with a MIX baseboard, provides high performance term inal server capability for MULTIBUS II systems. The MIX 450 module, as a single module on

Multibus ii protocol

Abstract: 82389 Multibus arbitration protocol 82389 Message Passing Coprocessor A Multibus II Bus IEEE-1296
Contextual Info: in te i 82389 MESSAGE PASSING COPROCESSOR A MULTIBUS II BUS INTERFACE CONTROLLER • Highly Integrated VLSI Device — Single-Chip Interface for the Parallel System Bus IEEE 1296 — Interrupt Handling/Bus Arbitration Functions — Dual-Buffer Input and Output DMA