application of programmable array logic
Abstract: No abstract text available
Text: Basic Design with PLDs Advanced Micro Devices INTRODUCTION The Programmable Array Logic device, commonly known as the PAL device, was invented at Monolithic Memories in 1978. The concept for this revolutionary type of device sprang forth as a simple solution to the
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Monolithic Memories
Abstract: PLE5P16 PLE6P16 Monolithic Memories PROM programming MONOLITHIC MEMORIES PROM
Text: KHI Monolithic PLE5P16 PLE6P16 Programmable Logic Element Family REVISED Memories / / / / / ////////////////////////////////////////ADVANCE INFORMATION Features/ Benefits Typical Applications • Programmable replacement lor conventional TTL logic • Address decoding
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PLE5P16
PLE6P16
24-pin
28-pin
PLE5P16Â
PLE6P16
PLE5P16
ii27iR5i
Monolithic Memories
Monolithic Memories PROM programming
MONOLITHIC MEMORIES PROM
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block diagram 8x8 booth multiplier
Abstract: 25S558 comparison between intel 8086 and Zilog 80 microprocessor mPD7720 intel 8087 74S508 74S556 8x8 booth multiplier 67558-1 25S557
Text: Five New Ways to Go Forth and Multiply Chuck Hastings Our Multiplier Population Explosion Recently it has seemed as if every time you turned around Monolithic Memories was announcing another new multiplier. Want to catch your breath, and find out where each of these fits
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AR-107.
Southcon/82
block diagram 8x8 booth multiplier
25S558
comparison between intel 8086 and Zilog 80 microprocessor
mPD7720
intel 8087
74S508
74S556
8x8 booth multiplier
67558-1
25S557
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16X4/A4
Abstract: pal20s PAL20S10 pal8l14 PAL20RS8 S/PAL16A4 PAL8L14A
Text: MONOLITHIC MEMORIES INC t.8 t30Bm D QQQ5M“17 5 § D PAL Programmable Array Logic Devices HAL® (Hard Array Logic) Devices Features/Benefits In addition the PALVHAL device provides these options: • Reduces SSI/M SI chip count greater than 5 to 1 • Variable input/output pin ratio
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t30Bm
PAL20X8
PAL20X4
PAL20L10A
PAL20X10A
PAL20X8A
PAL20X4A
PAL20S10
PAL20RS10
PAL20RS8
16X4/A4
pal20s
PAL20S10
pal8l14
PAL20RS8
S/PAL16A4
PAL8L14A
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9P4M
Abstract: 10P4M 12P4M 12p8 PLE5P8 PLE8P8 8p4c t461 PLE5P8A
Text: MONOLITHIC MEMORIES INC tfl » e J b3D3mO □ OOS'tkS 3 f D r-'W ’ Programmable Logic Element PLE Circuit Fam ily Ordering Information Features/Benefits PLE5P8 A C N STD • Programmable replacement for conventional TTL logic TZPR O C ESSIN G T • Reduces 1C inventories and simplities their control
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A10A9A6'
9P4M
10P4M
12P4M
12p8
PLE5P8
PLE8P8
8p4c
t461
PLE5P8A
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wf vqc 10d
Abstract: TGS 2201 SMD W2T TRANSISTOR SMD W2T 72 EX5962 MMI PAL14L8 C57401j tms 6011 MIMI Ti PROM programming procedure w2t smd
Text: 2 Specialty Memory Products 1988 Data Book Advanced Micro Devices Monolithic ryisn Memories UliTlU A W h o lly O w n e d S u b s id ia ry o f A d v a n c e d M ic r o D e vice s a Advanced Micro Devices Sp ecialty Memory Products Data Book/Handbook Introduction
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06566C
06972D
06705D
wf vqc 10d
TGS 2201
SMD W2T
TRANSISTOR SMD W2T 72
EX5962
MMI PAL14L8
C57401j
tms 6011
MIMI Ti PROM programming procedure
w2t smd
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1024x8 PROM
Abstract: No abstract text available
Text: c, MmoHMb m Memories High Performance 1024x8 PROM 5 3 /6 3 S 8 8 0 5 3 /6 3 S 8 8 1 5 3 /6 3 S 8 8 1 A / / / / / / / / / ////////////////////////////////////A DVA NCE INFORMATION Features/ Benefits Applications • 8192-blt memory • Microprogram control stores
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1024x8
8192-blt
128x64
1024x8 PROM
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Monolithic Memories
Abstract: S485A 512x8 53S485 63S485 63S841
Text: High Performance 512x8 PROM TiW PROM Fam ily 5 3 /6 3 S 4 8 5 Features/Benefits Description • Upward pinout-compatible with higher density PROMs The 53S485 and 63S485 are 512x8 bipolar PROMs featuring low current PNP inputs, full Schottky clam ping, and three-state
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53/63S485
512x8
45-ns
24-pin
53S485
63S485
53/63S841
53/63S841A
Monolithic Memories
S485A
63S841
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generic prom programming
Abstract: 256x8 Monolithic Memories PROM programming
Text: High Performance 25 6x 8 PROM TiW PROM Family 63S285 Features/ Benefits Description • Replaces 24-pin 256x8 NiCr PROM 6336 The 63S285 is a 256x8 bipolar PROM featuring low-current PNP inputs, full Schottky clamping, and three-state outputs. The titanium-tungsten fuses store a logical low and are programmed
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24-pin
256x8
45-ns
63S285
63S285
generic prom programming
Monolithic Memories PROM programming
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Untitled
Abstract: No abstract text available
Text: High Performance 5 1 2 x 8 PROM TiW PROM Family 5 3 /6 3 S 4 8 0 5 3 /6 3 S 4 8 1 5 3 /6 3 S 4 8 1 A Features/ Benefits Description • 30 ns maximum access time The 53/63S480 and 53/63S481/A are 512x8 bipolar PROMs featuring low input current PNP inputs, full Schottky clamping,
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53/63S480
53/63S481/A
512x8
53S481A
53S480,
53S481
63S481A
63S480,
63S481
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Monolithic Memories PROM programming
Abstract: 512X8 53S485 63S485 generic prom programming
Text: High Perform ance 512x8 PROM TiW PROM Fam ily 5 3 /6 3 S 4 8 5 CSS485 Features/ Benefits Description • Upward pinout-compatible with higher density PROMs The 53S485 and 63S485 are 512x8 bipolar PRO M s featuring low current PNP inputs, full Schottky clamping, and three-state
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512x8
CSS485
45-ns
24-pin
53S485
63S485
Monolithic Memories PROM programming
generic prom programming
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Monolithic Memories PROM programming
Abstract: 63S1681
Text: High Perform ance 2 0 4 8 x 8 PROM TiW PROM Fam ily 53/63S 1681 5 3 /6 3 S 1 6 8 1 A Features/ Benefits Description • 35 n# maximum access time The 53/63S1681 is a high-speed 2Kx8 PROM which uses industry standard package and pin out. In addition, the device is
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16384-bit
53/63S
53/63S1681
24-pin
Monolithic Memories PROM programming
63S1681
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128x128
Abstract: 63S1641 53S1641 53S1641A 63S1641A
Text: High Performance 4096x4 PROM TiW PROM Fam ily 53/63S1641 53/63S1641A Features/Benefits Description • 35-ns maximum access time The 53/63S1641 features low input current PNP inputs, full Schottky clamping and three-state outputs. The titaniumtungsten fuses store a logical low and are programmed to the
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4096x4
53/63S1641
53/63S1641A
35-ns
53/63S1641
53/63S881
53/63S881A
53/63S1641A
128x128
63S1641
53S1641
53S1641A
63S1641A
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63S1681
Abstract: monolithic memories 53S1681 63S1681A 2048x8 53S1681A Monolithic Memories PROM programming
Text: High Performance 2 0 4 8 x 8 PROM TiW PROM Fam ily 53 /63S 1681 5 3 /6 3 S 1 6 8 1 A Features/Benefits Description • 35-ns maximum access time The 53/63S1681 is a high-speed 2Kx8 PROM which uses industry standard package and pin out. In addition, the device is
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2048x8
35-ns
16384-bit
53/63S1681
53/63S1681A
24-pin
53/63S1681A
53/63S3281
63S1681
monolithic memories
53S1681
63S1681A
53S1681A
Monolithic Memories PROM programming
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1024X4
Abstract: 53S440 53S441 53S441A 63S440 63S441 63S441A 63S481
Text: High Performance 1 0 2 4 x 4 PROM TiW PROM Family 5 3 /6 3 S 4 4 0 5 3 /6 3 S 4 4 1 5 3 /6 3 S 4 4 1 A Features/ Benefits Description • 35-ns maximum access time The 53/63S440 and 53/63S441/A are 1024x4 bipolar PROMs featuring low input current PNP inputs, full Schottky clamping
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53/63S440
1024x4
53/63S441
53/63S441A
35-ns
53/63S440
53/63S441/A
53/63S480
53/63S481A
53S440
53S441
53S441A
63S440
63S441
63S441A
63S481
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MMI 6309
Abstract: mmi 5349-1 MMI 63xx 6309-1 mmi 6349-1 6308 prom 6341 prom
Text: Generic NiCR PROM Fam ily 5 3 /6 3 X X -1 5 3 /6 3 X X -2 Features/Benefits Description • From 2048-bit to 8192-bit memory The 53/63XX series generic PROM fam ily offers a wide selection of size and organizations. The 8-bit wide PROMs range from 256x8 to 1024x8 in a wide selection of package sizes including the
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2048-bit
8192-bit
53/63XX
256x8
1024x8
24-pin
300-inch
MIL-M-38510)
51A-074
31A-064
MMI 6309
mmi 5349-1
MMI 63xx
6309-1
mmi 6349-1
6308 prom
6341 prom
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53DA441
Abstract: 53DA442 63DA441 63DA442 D442 Monolithic Memories PROM programming MONOLITHIC MEMORIES PROM
Text: 1 0 2 4 x 4 Diagnostic Registered PROM 5 3 /6 3 D A 4 4 1 5 3 /6 3 D A 4 4 2 Enables and Output Initialization Features/Benefits • Programmable asynchronous output initialization • Three-state outputs with two enables • Provides system diagnostic testing with system
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1024x4
53/63DA441
53/63DA442
24-pln
24-mA
53/63DA442
53/63DA441
53DA441
53DA442
63DA441
63DA442
D442
Monolithic Memories PROM programming
MONOLITHIC MEMORIES PROM
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Untitled
Abstract: No abstract text available
Text: 2048x8 Registered PROM 5 3 /6 3 R A 1 6 8 1 5 3 /6 3 R A 1 6 8 1 A ^ j w ith Asynchronous Enable Features/ Benefits Description • Synchronous output enable The 53/63RA1681 and 53/63RA1681A are 2Kx8 PROMs with on-chip “ D''-type registers. O utput enable control through an
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2048x8
53/63RA1681
53/63RA1681A
24-pin
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1024x4
Abstract: 1024X4 prom tS1820 53S441 63S441A 53S440 53S441A 63S440 63S441 generic prom programming
Text: High Performance 1 0 2 4 x 4 PROM TiW PROM Family 5 3 /6 3 S 4 4 0 5 3 /6 3 S 4 4 1 5 3 /6 3 S 4 4 1 A Features/ Benefits Description • 35-ns maximum access time The 53/63S440 and 53/63S441/A are 1024x4 bipolar PROMs featuring low input current PNP inputs, full Schottky clamping
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53/63S440
1024x4
53/63S441
53/63S441A
35-ns
53/63S440
53/63S441/A
63S441A
63S440,
1024X4 prom
tS1820
53S441
53S440
53S441A
63S440
63S441
generic prom programming
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53RS1681A
Abstract: 53DA1643 53RS1681 63RS1681 63RS1681A
Text: 2048x8 Registered PROM 5 3 /6 3 R S 1 6 8 1 5 3 /6 3 R S 1 6 8 1 A with Synchronous Enable Features/Benefits Description • Synchronous output enable The 53/63RS1681 and 53/63RS1681A are 2Kx8 PROMs w ith on -chip “ D” type registers, versatile output enable control
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2048x8
53/63RS1681
53/63RS1681A
24-pin
111nputs,
2048product
53/63RS1681
53/63RS1681A
53DA1643
53RS1681A
53RS1681
63RS1681
63RS1681A
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MONOLITHIC MEMORIES PROM
Abstract: No abstract text available
Text: 40 9 6 x 4 Diagnostic. h ,/w Registered PROM ^ 53D 1641 63D 1641 Asynchronous Enable Patent Pending Features/ Benefits Description • Asynchronous output enable The 53/63D1641 is a 4Kx4 PROM with registered three-state outputs and a shadow register for diagnostic capabilities.
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24-pin
24-mA
53/63D1641
53/63D1641
MONOLITHIC MEMORIES PROM
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63S881
Abstract: 53S881 53S881A 63S881A 1024x8 PROM
Text: High Performance 1 0 2 4 x 8 PROM TiW PROM Family 5 3 /6 3 S 8 8 1 5 3 /6 3 S 8 8 1 A Features/Benefits Description • 30-ns maximum access time The 53/63S881 and 53/63S881A are 1024x8 bipolar PROMs featuring low inpu t current PNP inputs, full S chottky clam ping,
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1024x8
53/63S881
53/63S881A
30-ns
24-pin
600-mil
53/63S881
53/63S881A
63S881
53S881
53S881A
63S881A
1024x8 PROM
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generic prom programming
Abstract: 63S1641A metal mask layout
Text: High Perform ance 4 0 9 6 x 4 PROM TiW PROM Fam ily 5 3 /6 3 S 1 6 4 1 5 3 /6 3 S 1 641A Features/ Benefits Description • 35 ns maximum access time The 53/63S1641 features low input current PNP inputs, full Schottky clamping and three-state outputs. The titaniumtungsten fuses store a logical low and are programmed to the
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53/63S1641
generic prom programming
63S1641A
metal mask layout
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74S450
Abstract: KU16 74s2708
Text: The Engineering Staff of TEXAS INSTRUMENTS INCORPORATED Sem iconductor Group Bipolar Memory Data Manual S EPT EM BER 1977 T exas In s t r u m e n t s ? 7 SCH O TTKYf SERIES 54S/74S PROGRAMMABLE READ-ONLY MEMORIES PROMS Choice of Three-State or Open Collector
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54S/74S
SN54S478
SN54S/74S476
74S450
KU16
74s2708
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