MIRA SDRAM Search Results

MIRA SDRAM Result Highlights (5)

Part	ECAD Model	Manufacturer	Description	Download	Buy
CSPT857CNLG		Renesas Electronics Corporation	2.5V - 2.6V PLL Differential 1:10 SDRAM Clock Driver
CSPT857DPAG		Renesas Electronics Corporation	2.5V-2.6V Phase Locked Loop Differential 1:10 SDRAM Clock Driver
CSPU877DBVG		Renesas Electronics Corporation	1.8V Phase Locked Loop Differential 1:10 SDRAM Clock Driver
CSPT857DBVG8		Renesas Electronics Corporation	2.5V-2.6V Phase Locked Loop Differential 1:10 SDRAM Clock Driver
CSPU877ANLG8		Renesas Electronics Corporation	1.8V Phase Locked Loop Differential 1:10 SDRAM Clock Driver

MIRA SDRAM Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
Untitled Abstract: No abstract text available Text: 512Mb DDR SDRAM Specification P3S12D30EF P3S12D40EF Deutron Electronics Corp. 8F, 68, Sec. 3, NanKing E. RD., Taipei 104, Taiwan, R.O.C. TEL: 886 -2-2517-7768 FAX: (886)-2-2517-4575 http://www.deutron.com.tw 512Mb DDR Synchronous DRAM P3S12D30/40EF DESCRIPTION	Original	PDF	512Mb P3S12D30EF P3S12D40EF P3S12D30/40EF P3S12D30EF 216-word P3S12D40EF 608-word 16-bit,
MIRA SDRAM Abstract: No abstract text available Text: 256Mb DDR SDRAM Specification P2S56D20CTP P2S56D30CTP P2S56D40CTP Deutron Electronics Corp. 8F, 68, SEC. 3, NANKING E. RD., TAIPEI 104, TAIWAN, R. O. C. TEL : 886-2-2517-7768 FAX : 886-2-2517-4575 http: // www.deutron.com.tw 256Mb DDR Synchronous DRAM P2S56D20CTP 4-bank x 16,777,216 - word x 4-bit	Original	PDF	256Mb P2S56D20CTP P2S56D30CTP P2S56D40CTP 16-bit) 200MHz MIRA SDRAM
P3S12D40ETP Abstract: No abstract text available Text: 512Mb DDR Synchronous DRAM P3S12D30/40ETP DESCRIPTION P3S12D30ETP is a 4-bank x 16,777,216-word x 8-bit, P3S12D40ETP is a 4-bank x 8,388,608-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output	Original	PDF	512Mb P3S12D30/40ETP P3S12D30ETP 216-word P3S12D40ETP 608-word 16-bit, P3S12D30/40ETP 200MHz,
p2v56s Abstract: No abstract text available Text: 256Mb Synchronous DRAM Specification P2V56S20BTP P2V56S30BTP P2V56S40BTP Deutron Electronics Corp. 8F, 68, SEC. 3, NANKING E. RD., TAIPEI 104, TAIWAN, R. O. C. TEL : 886-2-2517-7768 FAX : 886-2-2517-4575 http: // www.deutron.com.tw 256Mb Synchronous DRAM 256Mb Synchronous DRAM	Original	PDF	256Mb P2V56S20BTP P2V56S30BTP P2V56S40BTP 216-WORD 608-WORD p2v56s
Untitled Abstract: No abstract text available Text: 64Mb Synchronous DRAM Specification P2V64S20DTP P2V64S30DTP P2V64S40DTP Deutron Electronics Corp. 8F, 68, SEC. 3, NANKING E. RD., TAIPEI 104, TAIWAN, R. O. C. TEL : 886-2-2517-7768 FAX : 886-2-2517-4575 http: // www.deutron.com.tw 64Mb Synchronous DRAM P2V64S20DTP 4-BANK x 4,194,304-WORD x 4-BIT	Original	PDF	P2V64S20DTP P2V64S30DTP P2V64S40DTP 304-WORD 152-WORD 576-WORD 16-BIT)
Untitled Abstract: No abstract text available Text: Deutron Electronics Corporation P2S56D50CF Preliminary 256M Double Data Rate Synchronous DRAM PRELIMINARY Some of contents are subject to change without notice. DESCRIPTION The P2S56D50CF is a 128M bits Double Data Rate(DDR) SDRAM organized as 2,097,154 words x	Original	PDF	P2S56D50CF P2S56D50CF 144-pin
mira p2s56d40btp Abstract: No abstract text available Text: 256Mb DDR SDRAM Specification P2S56D20BTP-5,-6,-75 P2S56D30BTP-5,-6,-75 P2S56D40BTP-5,-6,-75 256Mb DDR Synchronous DRAM P2S56D20BTP -5,-6,-75 4-bank x 16,777,216 - word x 4-bit P2S56D30BTP -5,-6,-75(4-bank x 8,388,608 - word x 8-bit) P2S56D40BTP -5,-6,-75(4-bank x 4,194,304 - word x 16-bit)	Original	PDF	256Mb P2S56D20BTP-5 P2S56D30BTP-5 P2S56D40BTP-5 P2S56D20BTP P2S56D30BTP P2S56D40BTP 16-bit) mira p2s56d40btp
a2v28s40 Abstract: A2V28S MIRA SDRAM p2v28s40dtp sdram 4 bank 4096 16 P2V28S20ATP-7 P2V28S20DTP-7 P2V28S30ATP-7 P2V28S40ATP-7 a2v28s40atp Text: 128Mb Synchronous DRAM P2V28S20ATP-7,-75,-8 4-BANK x 8,388,608-WORD x 4-BIT P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT) 128Mb SDRAM Specification P2V28S20DTP-7,-75,-8 P2V28S30DTP-7,-75,-8	Original	PDF	128Mb P2V28S20ATP-7 608-WORD P2V28S30ATP-7 304-WORD P2V28S40ATP-7 152-WORD 16-BIT) P2V28S20DTP-7 a2v28s40 A2V28S MIRA SDRAM p2v28s40dtp sdram 4 bank 4096 16 a2v28s40atp
MIRA SDRAM Abstract: No abstract text available Text: 128Mb Synchronous DRAM Specification P2V28S30CTP P2V28S40CTP Deutron Electronics Corp. 8F, 68, Sec. 3, NanKing E. RD., Taipei 104, Taiwan, R.O.C. TEL: 886 -2-2517-7768 FAX: (886)-2-2517-4575 1 P2V28S30CTP/ P2V28S40CTP 128M Single Data Rate Synchronous DRAM	Original	PDF	128Mb P2V28S30CTP P2V28S40CTP P2V28S30CTP/ P2V28S30CTP 304-word P2V28S40CTP 152-word 16-bit. MIRA SDRAM
Untitled Abstract: No abstract text available Text: Deutron Electronics Corp. P2S28D30/40CTP 128M Double Data Rate Synchronous DRAM PRELIMINARY Some of contents are subject to change without notice. DESCRIPTION P2S28D30CTP is a 4-bank x 4,194,304-word x 8bit,P2S28D40CTP is a 4-bank x 2,097,152-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface. All control and address signals	Original	PDF	P2S28D30/40CTP P2S28D30CTP 304-word P2S28D40CTP 152-word 16bit P2S28D30/40CTP
8251 intel microcontroller architecture Abstract: vhdl source code for 8086 microprocessor 8251 usart verilog coding for asynchronous decade counter verilog code for 8254 timer verilog code for median filter 8251 uart vhdl SERVICE MANUAL oki 32 lcd tv verilog code for iir filter VHDL CODE FOR HDLC controller Text: ALTERA MEGAFUNCTION PARTNERS PROGRAM Catalog About this Catalog ® May 1996 AMPP Catalog Contents This catalog provides an introduction to the Altera Megafunction Partners Program, a description of each AMPP megafunction, and a listing of corporate profiles and contact information for each AMPP	Original	PDF
verilog code for 2D linear convolution Abstract: verilog code for GPS correlator vhdl code numeric controlled oscillator pipeline rx UART AHDL design verilog code car parking free verilog code of median filter verilog code for 2D linear convolution filtering verilog code for median filter 16 QAM modulation verilog code LED Dot Matrix vhdl code Text: AMPP Catalog February 1997 AMPP Catalog February 1997 M-CAT-AMPP-02 Altera, AHDL, AMPP, OpenCore, MAX, MAX+PLUS, MAX+PLUS II, FLEX, FLEX 10K, FLEX 8000, MAX 9000, MAX 7000, EPF10K10, EPF10K20, EPF10K30, EPF10K40, EPF10K50, EPF10K70, EPF10K100, EPF8282, EPF82828A, EPF8452, EPF8452A, EPF8636A, EPF8820, EPF8820A, EPF8118,	Original	PDF	M-CAT-AMPP-02 EPF10K10, EPF10K20, EPF10K30, EPF10K40, EPF10K50, EPF10K70, EPF10K100, EPF8282, EPF82828A, verilog code for 2D linear convolution verilog code for GPS correlator vhdl code numeric controlled oscillator pipeline rx UART AHDL design verilog code car parking free verilog code of median filter verilog code for 2D linear convolution filtering verilog code for median filter 16 QAM modulation verilog code LED Dot Matrix vhdl code
free vHDL code of median filter Abstract: free verilog code of median filter verilog code for UART with BIST capability verilog code for 2D linear convolution rx UART AHDL design verilog code for 2D linear convolution filtering vhdl median filter verilog code for median filter 8051 interface ppi 8255 vhdl code direct digital synthesizer Text: AMPP Catalog February 1997 About this Catalog February 1997 AMPP Catalog Contents This catalog describes the Altera® Megafunction Partners Program AMPP . The catalog also provides megafunction descriptions and partner profiles for each AMPP partner. The information in this catalog is	Original	PDF
japanese transistor manual substitution Abstract: M30622F8PGP M30622MEP-XXXGP ROE000080KCE00 M30833FJFP programmer M30622F8PFP M30624MGN-XXXGP M3062G m30700fk S550-MFW-1U Text: 2005.9 Renesas Microcontroller M16C Family www.renesas.com The M16C Platform - The Industry's Most Extensive, Powerful, and Easy to Use 16-bits Microcontroller Solutions Having trouble reducing product costs and development costs and periods? Greater functionality	Original	PDF	16-bits M162265-6688, REJ01B0001-0500 japanese transistor manual substitution M30622F8PGP M30622MEP-XXXGP ROE000080KCE00 M30833FJFP programmer M30622F8PFP M30624MGN-XXXGP M3062G m30700fk S550-MFW-1U

gcu 101 setting manual Abstract: No abstract text available Text: User's Manual The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. SH7724 32 User’s Manual: Hardware Renesas 32-Bit RISC Microcomputer SH7780 Series R8A7724 Cover [Portions omitted in accordance with NDA]	Original	PDF	SH7724 32-Bit SH7780 R8A7724 ope00, R01UH0174EJ0200 REJ09B0560-0100) gcu 101 setting manual
ALC100 Abstract: ST CD C226 VM036 BK1606 COD-51 LS-120 WD62 L420 eef 1208 PA6 GF 10 MD10 Text: D i a g r a m s M a in b o a r d G T LH W 3 b TLH A 6 T LH W S G TL H i« G T L H tf? GT L HA#6 \ U . tq : 02: I4 n : « ; K1 . ji ; s . m : G r. h i; » : pi . H . r ; E l, 0« . IB . 0) E2, IS . w . f t , ci 83 . A3 02, 2 1; Ai AS 84, C5 , g t lh w s	OCR Scan	PDF	0UF/16V ALC100 ST CD C226 VM036 BK1606 COD-51 LS-120 WD62 L420 eef 1208 PA6 GF 10 MD10
Untitled Abstract: No abstract text available Text: IBM0317329N IBM0317329P Advance 512K x 32 Synchronous Graphics RAM Features • Single 3.3V + 0.3 • Fully synchronous; all signals registered on pos itive edge ot system clock • 100-pin LQFP 0.65mm lead pitch • Internal pipelined operation; column address	OCR Scan	PDF	IBM0317329N IBM0317329P cycles/16ms cycles/128ms